Patents by Inventor Praveen NARENDRANATH

Praveen NARENDRANATH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Area-efficient metal-programmable pulse latch design
    Patent number: 9564881
    Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: February 7, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Qi Ye, Steven James Dillen, Animesh Datta, Zhengyu Duan, Satyanarayana Sahu, Praveen Narendranath
  • AREA-EFFICIENT METAL-PROGRAMMABLE PULSE LATCH DESIGN
    Publication number: 20160344374
    Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.
    Type: Application
    Filed: May 22, 2015
    Publication date: November 24, 2016
    Inventors: Qi YE, Steven James DILLEN, Animesh DATTA, Zhengyu DUAN, Satyanarayana SAHU, Praveen NARENDRANATH