Abstract: A host system for generating a software built-in self-test engine (SBE) is provided for enabling on-chip generation and application of a re-generative functional test on a complex device such as a microprocessor under test. The host system comprises user directives provided to indicate user desired actions; instruction information provided to define a suite of instructions; and a SBE generation tool arranged to generate a software built-in self-test engine (SBE) based on the user directives, the instruction information and device constraints, for subsequent storage on-board of a complex device such as a microprocessor under test and activation of a re-generative functional test on the complex device under test (DUT).

Abstract: A method and apparatus for providing a scan cell having a first input coupled to receive a data, a data output and a scan output. The scan cell being capable of transferring data to said scan output in response to a first scan clock and a second scan clock without requiring any timing-sensitive control signals.

Abstract: A method and apparatus comprising a first circuit configured to receive a mode signal and generate a first signal and a second signal, the first circuit being configured to deassert the first signal and the second signal when the mode signal is in a first state; a first scan cell configured to latch a first input in response to the first signal and to latch a second input in response to a third signal to produce a first latched signal on a first output, the first scan cell configured to drive a second output in response to a fourth signal, wherein the second input and the second output are coupled to a scan chain; a dynamic circuit having a dynamic node, the dynamic circuit being configured to receive the first output and the second signal, to precharge the dynamic node in response to the second signal being deasserted, and produce a data on the third output in response to the second signal being asserted and the state of the dynamic node; and a second cell configured to latch the data in response to the seco

Abstract: A method and apparatus for using weighted random patterns in a partial scan test. A computer generates deterministic patterns on the partial scan design. Deterministic patterns that have the same number of capture clocks between adjacent scan loads are grouped together into pattern groups. A computer then determines a set of weights corresponding to each of the pattern groups. A tester then uses these weights as a filter to weighted random test patterns and applies these filtered weighted random test patterns along with the appropriate number of capture clock pulses to a device under test.

Abstract: A method and apparatus for using a test signal being computed by applying a combinational test pattern generation tool to a model of the apparatus in which at least one of an at least one sequential device is modelled as a non-sequential device, the apparatus having a first scan cell configured to receive the test signal and drive a first signal in response to a first clock phase; a sequential logic block having the at least one sequential device, the sequential logic block being configured to generate a second signal, at least one of the at least one sequential device being a non-scan cell.