Patents by Inventor Praveen Raghavan
Praveen Raghavan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105727Abstract: Various structures that implement topside metal routing and backside metal routing in combination with vertical transistors are disclosed. The various structures include cells that form inverter devices, NAND devices, and MUX (multiplexer) devices. The disclosed cells include two or four vertical transistors with various connections made to the transistors that include either connected gate logic for inverter and NAND devices or disconnected gate logic for MUX devices.Type: ApplicationFiled: August 11, 2023Publication date: March 28, 2024Inventors: Xin Miao, Praveen Raghavan, Thomas Hoffmann, Saurabh P. Sinha
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Publication number: 20240105617Abstract: Various structures that implement topside metal routing and backside metal routing in combination with vertical transistors are disclosed. The various structures include a building block cell with a metal contact layer between the backside metal routing and the vertical transistors. Various connections can be made within the building block cell to form more complex structures such as, but not limited to, inverter devices, NAND devices, and MUX (multiplexer) devices.Type: ApplicationFiled: August 11, 2023Publication date: March 28, 2024Inventors: Xin Miao, Praveen Raghavan, Thomas Hoffmann
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Publication number: 20230299068Abstract: A cell layout that may be implemented in FinFET devices or other FET devices is disclosed. The cell layout includes a control signal route that passes from a first device into backside layers and then underneath a second device. The control signal route then routes back to topside metal layers through inactive transistors that are implemented as via structures on the other side of the second device. Connection to the gate of the second device may then be completed through the topside metal layers. The disclosed control signal route provides a low resistance path that reduces RC delay in the devices in the cell layout.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Inventors: Sambasivan Narayan, Praveen Raghavan
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Publication number: 20230299001Abstract: A standard cell layout that may be implemented in FinFET devices or nanosheet FET devices is disclosed. The standard cell layout includes power supply connections from both a topside metal layer and a backside metal layer. A device in the standard cell may be connected to both the topside metal layer and the backside metal layer. Source/drain regions of the device may be connected the metal layers using via contacts within the standard cell layout. Connections to power supply rails from the topside metal layer and the backside metal layer may also be included in the standard cell layout. The rails may be connected to a power supply such that the power supply provides power to the device through both the topside and backside metal layers.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Inventors: Sambasivan Narayan, Praveen Raghavan
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Patent number: 11475101Abstract: A method and hardware system for mapping an input map of a convolutional neural network layer to an output map are disclosed. An array of processing elements are interconnected to support unidirectional dataflows through the array along at least three different spatial directions. Each processing element is adapted to combine values of dataflows along different spatial directions into a new value for at least one of the supported dataflows. For each data entry in the output map, a plurality of products from pairs of weights of a selected convolution kernel and selected data entries in the input map is provided and arranged into a plurality of associated partial sums. Products associated with a same partial sum are accumulated on the array and accumulated on the array into at least one data entry in the output map.Type: GrantFiled: November 15, 2019Date of Patent: October 18, 2022Assignee: Imec VZWInventors: Francky Catthoor, Praveen Raghavan, Dimitrios Rodopoulos, Mohit Dandekar
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Patent number: 10802743Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.Type: GrantFiled: July 5, 2018Date of Patent: October 13, 2020Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Francky Catthoor, Praveen Raghavan, Daniele Garbin, Dimitrios Rodopoulos, Odysseas Zografos
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Patent number: 10797224Abstract: The disclosed technology generally relates to magnetoresistive devices, and more particularly to a magnetic tunnel junction (MTJ) device formed in an interconnection structure, and to a method of integrating the (MTJ) device in the interconnection structure. According to an aspect, a device includes a first interconnection level including a first dielectric layer and a first set of conductive paths arranged in the first dielectric layer, a second interconnection level arranged on the first connection level and including a second dielectric layer and a second set of conductive paths arranged in the second dielectric layer, and a third interconnection level arranged on the second interconnection level and including a third dielectric layer and a third set of conductive paths arranged in the third dielectric layer.Type: GrantFiled: February 23, 2018Date of Patent: October 6, 2020Assignees: IMEC vzw, Katholieke Universiteit LeuvenInventors: Praveen Raghavan, Davide Francesco Crotti, Raf Appeltans
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Publication number: 20200159809Abstract: A method and hardware system for mapping an input map of a convolutional neural network layer to an output map are disclosed. An array of processing elements are interconnected to support unidirectional dataflows through the array along at least three different spatial directions. Each processing element is adapted to combine values of dataflows along different spatial directions into a new value for at least one of the supported dataflows. For each data entry in the output map, a plurality of products from pairs of weights of a selected convolution kernel and selected data entries in the input map is provided and arranged into a plurality of associated partial sums. Products associated with a same partial sum are accumulated on the array and accumulated on the array into at least one data entry in the output map.Type: ApplicationFiled: November 15, 2019Publication date: May 21, 2020Inventors: Francky Catthoor, Praveen Raghavan, Dimitrios Rodopoulos, Mohit Dandekar
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Patent number: 10510774Abstract: An integrated circuit (IC) power distribution network is disclosed. In one aspect, the IC includes a stack of layers formed on a substrate. The IC includes standard cells with parallel gate structures oriented in a direction y. Each cell includes an internal power pin for supplying a reference voltage to the cell. The stack includes metal layers in which lines are formed to route signals between cells. The lines in each metal layer have a preferred orientation that is orthogonal to that of the lines in an adjacent metal layer. A first layer is the lowest metal layer that has y as a preferred orientation while also providing routing resources for signal routing between the cells. A second layer is the nearest metal layer above this first layer. The IC includes a power distribution network for delivering the reference voltage to the power pin.Type: GrantFiled: April 5, 2017Date of Patent: December 17, 2019Assignee: IMEC vzwInventors: Peter Debacker, Praveen Raghavan, Vassilios Constantinos Gerousis
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Patent number: 10355128Abstract: A semiconductor device is disclosed that includes a substrate and at least a first, second, third, and fourth vertical transistor supported by the substrate. Each transistor comprises a vertical channel, a polarity gate electrode forming a polarity gate adapted to act on a first portion of the channel to affect a polarity of the channel, and a control gate electrode forming a control gate adapted to act on a second portion of the channel to control the electrical conductivity of the channel. The polarity gate electrode and the control gate electrode of each one of the transistors extend laterally from their respective gate and in mutually opposite directions, and the transistors are laterally spaced from each other and arranged such that the control gate electrodes of the first and third transistor face each other and the control gate electrodes of the second and fourth transistor face each other.Type: GrantFiled: December 8, 2017Date of Patent: July 16, 2019Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&DInventors: Praveen Raghavan, Odysseas Zografos
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Patent number: 10332588Abstract: In an aspect of the disclosed technology, a SRAM device includes a first stack of transistors and a second stack of transistors arranged on a substrate. Each of the first and second stacks includes a pull-up transistor, a pull-down transistor and a pass transistor, where each of the transistors includes a horizontally extending channel. In each of the first and second stacks, the pull-up transistor and the pull-down transistor have a common gate electrode extending vertically therebetween, and the pass transistor has a gate electrode separated from the common gate electrode. A source/drain of each of the pull-up transistor and the pull-down transistor and a source/drain of the pass transistor included in one of the first stack and the second stack are electrically interconnected with the common gate electrode of the pull-up transistor and the pull-down transistor included in the other of the first stack and the second stack.Type: GrantFiled: December 21, 2017Date of Patent: June 25, 2019Assignees: IMEC vzw, Vrije Universiteit BrusselInventors: Trong Huynh Bao, Julien Ryckaert, Praveen Raghavan, Pieter Weckx
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Publication number: 20190034111Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.Type: ApplicationFiled: July 5, 2018Publication date: January 31, 2019Inventors: Francky Catthoor, Praveen Raghavan, Daniele Garbin, Dimitrios Rodopoulos, Odysseas Zografos
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Patent number: 10147637Abstract: A method of forming conductive paths and vias is disclosed. In one aspect, patterns of a hard mask layer are transferred into a dielectric layer by etching to form trenches. The trenches define locations for conductive paths of an upper metallization level. At least one trench is interrupted in a longitudinal direction by a block portion of the hard mask layer, the block portion defining the tip-to-tip location of a pair of the conductive paths to be formed. The trenches extend partially through the dielectric layer in regions exposed by the hard mask layer, thereby deepening first and the second holes to extend completely through the dielectric layer. After removing the hard mask layer, the deepened first and second holes and the trenches are filled with a conductive material to form the conductive paths in the trenches and to form the vias in the deepened first and second holes.Type: GrantFiled: February 5, 2018Date of Patent: December 4, 2018Assignee: IMEC vzwInventors: Youssef Drissi, Ryan Ryoung han Kim, Stephane Lariviere, Praveen Raghavan, Darko Trivkovic
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Patent number: 10127961Abstract: Three transistor two junction magnetoresistive random-access memory (MRAM) bit cells provided. An example MRAM bit cell includes a first magnetic tunnel junction, MTJ, connected to a first bit line. The MRAM bit cell also includes a second MTJ connected to a second bit line. In addition, the MRAM bit cell includes a first transistor connected to the first MTJ and to a ground conductor. The MRAM bit cell further includes a second transistor connected to the second MTJ and to the ground conductor. Additionally, the MRAM bit cell includes a third transistor connected to the first transistor and to the second transistor.Type: GrantFiled: December 2, 2016Date of Patent: November 13, 2018Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Raf Appeltans, Praveen Raghavan
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Publication number: 20180261497Abstract: A method of forming conductive paths and vias is disclosed. In one aspect, patterns of a hard mask layer are transferred into a dielectric layer by etching to form trenches. The trenches define locations for conductive paths of an upper metallization level. At least one trench is interrupted in a longitudinal direction by a block portion of the hard mask layer, the block portion defining the tip-to-tip location of a pair of the conductive paths to be formed. The trenches extend partially through the dielectric layer in regions exposed by the hard mask layer, thereby deepening first and the second holes to extend completely through the dielectric layer. After removing the hard mask layer, the deepened first and second holes and the trenches are filled with a conductive material to form the conductive paths in the trenches and to form the vias in the deepened first and second holes.Type: ApplicationFiled: February 5, 2018Publication date: September 13, 2018Inventors: Youssef Drissi, Ryan Ryoung han Kim, Stephane Lariviere, Praveen Raghavan, Darko Trivkovic
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Patent number: 10073802Abstract: The disclosure relates to a data communication network connecting a plurality of computation clusters. The data communication network is arranged for receiving via N data input ports, N>1, input signals from first clusters of the plurality and for outputting output signals to second clusters of the plurality via M data output ports, M>1. The communication network includes a segmented bus network for interconnecting clusters of the plurality and a controller arranged for concurrently activating up to P parallel data busses of the segmented bus network, thereby forming bidirectional parallel interconnections between P of the N inputs, P<N, and P of the M outputs, P<M, via paths of connected and activated segments of the segmented bus network. The segments are linked by segmentation switches. The N data input ports and the M data output ports are connected via stubs to a subset of the segmentation switches.Type: GrantFiled: August 29, 2016Date of Patent: September 11, 2018Assignees: IMEC VZW, Stichting IMEC NederlandInventors: Francky Catthoor, Praveen Raghavan
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Publication number: 20180248111Abstract: The disclosed technology generally relates to magnetoresistive devices, and more particularly to a magnetic tunnel junction (MTJ) device formed in an interconnection structure, and to a method of integrating the (MTJ) device in the interconnection structure. According to an aspect, a device includes a first interconnection level including a first dielectric layer and a first set of conductive paths arranged in the first dielectric layer, a second interconnection level arranged on the first connection level and including a second dielectric layer and a second set of conductive paths arranged in the second dielectric layer, and a third interconnection level arranged on the second interconnection level and including a third dielectric layer and a third set of conductive paths arranged in the third dielectric layer.Type: ApplicationFiled: February 23, 2018Publication date: August 30, 2018Inventors: Praveen Raghavan, Davide Francesco Crotti, Raf Appeltans
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Patent number: 10043798Abstract: A semiconductor circuit comprises a Front End of Line (FEOL) comprising a plurality of transistors, each of which having a source region, a drain region and a gate region arranged between the source region and the drain region and comprising a gate electrode. The semiconductor circuit also comprises a buried interconnect that is arranged in the FEOL and electrically connected to the gate region from below through a bottom contact portion of the gate electrode. By using a buried interconnect the routing of the circuit may be facilitated.Type: GrantFiled: August 25, 2016Date of Patent: August 7, 2018Assignee: IMEC VZWInventors: Stefan Cosemans, Praveen Raghavan, Steven Demuynck, Julien Ryckaert
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Patent number: 10019361Abstract: The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. The memory hierarchy includes at least a level 1, referred to as L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB). The buffer structure includes a plurality of interconnected wide registers with an asymmetric organization, wider towards the non-volatile memory unit than towards a data path connectable to the processor. The buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the L1 data memory and the buffer structure (L1-VWB) by the processor.Type: GrantFiled: August 29, 2016Date of Patent: July 10, 2018Assignee: IMEC VZWInventors: Francky Catthoor, Praveen Raghavan, Matthias Hartmann, Komalan Manu Perumkunnil, Jose Ignacio Gomez, Christian Tenllado
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Publication number: 20180174642Abstract: The disclosed technology generally relates to semiconductor memory devices, and more particularly to a static random access memory (SRAM) device. One aspect of the disclosed technology is a bit cell for a static random access memory (SRAM) comprising: a first and a second vertical stack of transistors arranged on a substrate. Each stack includes a pull-up transistor, a pull-down transistor and a pass transistor, each transistor including a horizontally extending channel, the pull-up transistor and the pull-down transistor having a common gate electrode extending vertically between the pull-up transistor and the pull-down transistor and the pass transistor having a gate electrode being separate from the common gate electrode. A source/drain of the pull-up transistor and of the pull-down transistor of the first stack, a source/drain of the pass transistor of the first stack and the common gate electrode of the pull-up and pull-down transistors of the second stack are electrically interconnected.Type: ApplicationFiled: December 21, 2017Publication date: June 21, 2018Inventors: Trong Huynh Bao, Julien Ryckaert, Praveen Raghavan, Pieter Weckx