Patents by Inventor Praveen Raghuraman
Praveen Raghuraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11940490Abstract: The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.Type: GrantFiled: November 18, 2022Date of Patent: March 26, 2024Assignee: QUALCOMM IncorporatedInventor: Praveen Raghuraman
-
Publication number: 20230078568Abstract: The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.Type: ApplicationFiled: November 18, 2022Publication date: March 16, 2023Inventor: Praveen RAGHURAMAN
-
Patent number: 11531061Abstract: The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.Type: GrantFiled: August 3, 2020Date of Patent: December 20, 2022Assignee: QUALCOMM IncorporatedInventor: Praveen Raghuraman
-
Patent number: 11455221Abstract: A memory includes an error detection circuit that identifies a faulty feature in an array of memory cells within the memory. A redundancy enable circuit functions to replace the faulty feature with a redundant feature. The error detection circuit and the redundancy enable circuit function concurrently with a read operation on the array of memory cells.Type: GrantFiled: September 18, 2020Date of Patent: September 27, 2022Assignee: QUALCOMM IncorporatedInventor: Praveen Raghuraman
-
Publication number: 20220034965Abstract: The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.Type: ApplicationFiled: August 3, 2020Publication date: February 3, 2022Inventor: Praveen RAGHURAMAN
-
Publication number: 20210133063Abstract: A memory includes an error detection circuit that identifies a faulty feature in an array of memory cells within the memory. A redundancy enable circuit functions to replace the faulty feature with a redundant feature. The error detection circuit and the redundancy enable circuit function concurrently with a read operation on the array of memory cells.Type: ApplicationFiled: September 18, 2020Publication date: May 6, 2021Inventor: Praveen RAGHURAMAN
-
Patent number: 10522236Abstract: A method and apparatus for repairing a memory is provided. At least one memory is tested using a production test pattern. After the production test, a passing or failing status is determined for each memory tested. This determination may be made using a built-in repair analysis (BIRA) program. After the analysis the location of each failing memory is determined. A fuse register pattern is then determined for the failing memory, and at least one fuse is blown to repair the failed memory. The repair utilizes at least one of the redundant memories present in the semiconductor device. The apparatus includes a semiconductor device having repairable memories, a fuse programmable read-only memory (FPROM) that contains multiple redundant memories, and a fuse box memory repair apparatus that is in communication with the FRPOM and the multiple repairable memories.Type: GrantFiled: March 25, 2016Date of Patent: December 31, 2019Assignee: QUALCOMM IncorporatedInventors: Praveen Raghuraman, Vaishnavi Sundaralingam, Madhura Hegde, Nikhil Sudhakaran
-
Publication number: 20180259578Abstract: A BIST circuit is provided with modes of operation in which the BIST procedure for a circuit-under-test occurs at a system clock rate for the circuit-under-test that is greater than a test clock rate for the BIST circuit.Type: ApplicationFiled: January 4, 2018Publication date: September 13, 2018Inventor: Praveen Raghuraman
-
Publication number: 20180005663Abstract: A method and apparatus for dynamic memory mode testing is provided. The method begins when an electronic device is reset before testing begins. A BIST mode is selected and then input to a BIST apparatus. The BIST mode is then performed and test results recorded. An additional BIST mode is then selected and testing using the additional BIST mode begins immediately. The apparatus includes a clock divider, a BIST controller in communication with the clock divider; a dynamic memory test module in communication with the clock divider, BIST controller and memory; and a low voltage test access port in communication with the BIST controller for receiving test output data from the BIST controller. The dynamic memory test module comprises: at least two AND gates in communication with at least three multiplexers.Type: ApplicationFiled: June 29, 2016Publication date: January 4, 2018Inventors: Praveen Raghuraman, Nikhil Sudhakaran
-
Publication number: 20170278583Abstract: A method and apparatus for repairing a memory is provided. At least one memory is tested using a production test pattern. After the production test, a passing or failing status is determined for each memory tested. This determination may be made using a built-in repair analysis (BIRA) program. After the analysis the location of each failing memory is determined. A fuse register pattern is then determined for the failing memory, and at least one fuse is blown to repair the failed memory. The repair utilizes at least one of the redundant memories present in the semiconductor device. The apparatus includes a semiconductor device having repairable memories, a fuse programmable read-only memory (FPROM) that contains multiple redundant memories, and a fuse box memory repair apparatus that is in communication with the FRPOM and the multiple repairable memories.Type: ApplicationFiled: March 25, 2016Publication date: September 28, 2017Inventors: Praveen Raghuraman, Vaishnavi Sundaralingam, Madhura Hegde, Nikhil Sudhakaran
-
Patent number: 9711241Abstract: Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.Type: GrantFiled: April 1, 2015Date of Patent: July 18, 2017Assignee: QUALCOMM IncorporatedInventors: Ashutosh Anand, Shankarnarayan Bhat, Nikhil Sudhakaran, Praveen Raghuraman, Nishi Bhushan Singh, Anand Bhat, Abhinav Kothiala, Sanjay Muchini, Arun Balachandar, Devadatta Bhat
-
Publication number: 20160293272Abstract: Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.Type: ApplicationFiled: April 1, 2015Publication date: October 6, 2016Inventors: Ashutosh Anand, Shankarnarayan Bhat, Nikhil Sudhakaran, Praveen Raghuraman, Nishi Bhushan Singh, Anand Bhat, Abhinav Kothiala, Sanjay Muchini, Arun Balachandar, Devadatta Bhat
-
Publication number: 20160077151Abstract: A method and apparatus for testing secure blocks is provided. The method begins when instructions for testing a secure memory are loaded using a parallel testing interface. Instructions for testing the non-secure memory may be resident on the device as Built-In-Self-Test (BIST) instructions. In that case, the instructions are then accessed through the standard test access. Testing occurs simultaneously for the secure memory and the non-secure memory using both the parallel interface and the standard test interface. Testing both the secure memory blocks and the non-secure memory blocks using the parallel and standard test interfaces saves time during the test process.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Ashutosh Anand, Shankarnarayan Bhat, Arun Balachandar, Nikhil Sudhakaran, Praveen Raghuraman, Devadatta Bhat, Sanjay Muchini
-
Publication number: 20140258509Abstract: Particular network usage information representing network activity of a particular device on a network is received. The particular network usage information is associated with a network context, the network context representing circumstances of the network activity of the particular device. The network context is associated with a particular network perspective, the network particular perspective representing a network activity of a group of devices on the network. The particular network perspective is rendered into an object, the object being configured to present the particular network perspective in a graphical user interface.Type: ApplicationFiled: February 28, 2014Publication date: September 11, 2014Applicant: AEROHIVE NETWORKS, INC.Inventors: Praveen Raghuraman, Weimin Du
-
Patent number: 7693742Abstract: A system, method, and computer program product are provided for charging for network analysis. Initially, network traffic information is collected utilizing a plurality of agents. Next, the network traffic information is collected utilizing a plurality of host controllers coupled to the agents. The network traffic information may then be reported to a user utilizing a plurality of zone controllers coupled to the host controllers. In use, a reoccurring fee associated with the reporting may be determined based on a number of the agents, the host controllers, and/or the zone controllers.Type: GrantFiled: September 13, 2007Date of Patent: April 6, 2010Assignee: McAfee, Inc.Inventors: Herbert V. Joiner, Praveen Raghuraman, Ravi Verma
-
Patent number: 7483861Abstract: A system, method, and computer program product are provided for charging for network analysis. Initially, network traffic information is collected utilizing a plurality of agents. Next, the network traffic information is collected utilizing a plurality of host controllers coupled to the agents. The network traffic information may then be reported to a user utilizing a plurality of zone controllers coupled to the host controllers. In use, a reoccurring fee associated with the reporting may be determined based on a number of the agents, the host controllers, and/or the zone controllers.Type: GrantFiled: December 21, 2001Date of Patent: January 27, 2009Assignee: McAfee, Inc.Inventors: Herbert V. Joiner, Praveen Raghuraman, Ravi Verma
-
Patent number: 6941358Abstract: A system, method and computer program product are provided for reporting on network analysis. Initially, network traffic information is collected utilizing a plurality of agents installed in computers distributed among a plurality of zones. Next, the network traffic information collected from the agents associated with each zone is received at separate controllers. Next, a report on the network traffic information is sent from one of the controllers to a computer coupled thereto via a network.Type: GrantFiled: December 21, 2001Date of Patent: September 6, 2005Assignee: Networks Associates Technology, Inc.Inventors: Herbert V. Joiner, Praveen Raghuraman, Ken W. Elwell
-
Patent number: 6789117Abstract: A system, method, and computer program product are provided for analyzing a network utilizing an agent/host controller interface. Initially, an agent is sent an interval setting from a host controller. Such agent is adapted to transmit network traffic information based on the interval setting. Such network traffic information is then received from the agent in accordance with the interval setting.Type: GrantFiled: December 21, 2001Date of Patent: September 7, 2004Assignee: Networks Associates Technology, Inc.Inventors: Herbert V. Joiner, Ken W. Elwell, Ravi Verma, Praveen Raghuraman
-
Patent number: 6714513Abstract: A system, method and computer program product are provided for analyzing a network utilizing an agent. Initially, a signal is sent from a computer to a host controller utilizing a network. Next, a response to the signal is received from the host controller. Information is then collected relating to network traffic involving the computer based on the response. The information is subsequently sent to the host controller on a periodic basis.Type: GrantFiled: December 21, 2001Date of Patent: March 30, 2004Assignee: Networks Associates Technology, Inc.Inventors: Herbert V. Joiner, Ravi Verma, Praveen Raghuraman, Ken W. Elwell