Abstract: A method for managing packet header fields in a physical (PHY) layer includes: receiving, by a header descriptor array (HDA) of a PHY layer, a data packet and a status signal of the data packet; writing, by the HDA, a header field for the received data packet; storing, by the HDA, the written header field and the status signal of the data packet in a header field array; and fetching, by the HDA, the header field of the data packet by enabling parallel reading of a plurality of locations of the header field array, enabling transmission and re-transmission of the data packet.

Abstract: There is provided a method for managing the inter-operability data rate range of serializer/deserializer (Ser-Des) test chips. The method doubles the inter-operability data rate range of the Ser-Des test chip, reduces the skew on data pins, and thereby increases the performance in the inter-operability test of the Ser-Des test chip.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: Built-in-self-test (BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as a synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.

Abstract: Methods and systems for calibrating clock skew in a SerDes receiver. A method includes detecting a skew in a clock with respect to an edge of a reference clock, based on a value sampled by the clock and a value sampled by the reference clock at an edge of a data pattern, for a first Phase Interpolator (PI) code; determining a count of the skew from a de-serialized data word including outcome values obtained based on values sampled by the clock and values sampled by the reference clock at a predefined number of edges of the data pattern; obtaining a skew calibration code corresponding to the first PI code, from a binary variable obtained by accumulating an encoded variable to a previously generated binary variable; and calibrating the skew by performing a positive phase shift or a negative phase shift to the clock based on the skew calibration code.

Abstract: A method, a computer system, and a computer program product for detection of unintended dependencies between hardware design signals from pseudo-random number generator (PRNG) taps is provided. Embodiments of the present invention may include identifying one or more tap points in a design as an execution sequence. Embodiments of the present invention may include sampling the tap points by propagating the tap points in the design with different delays. Embodiments of the present invention may include defining observation points to identify tap collisions based on the tap points. Embodiments of the present invention may include identifying tap collisions. Embodiments of the present invention may include identifying one or more sources of the tap collisions in the design. Embodiments of the present invention may include eliminating the one or more sources of uninteresting tap collisions out of the tap collisions and filtering one or more of the tap collisions.

Abstract: The present disclosure provides systems and methods for performing built-in-self-test (BIST) operations without a dedicated clock source. The BIST operations are performed by receiver lanes of a multilane receiver system, wherein at least one receiver lane is configured as synthesized clock source for other receiver lanes configured to perform BIST operations. The at least one receiver lane configured as the synthesized clock source may generate a clock signal and provide the clock signal to the other receiver lanes performing the BIST operations. In some examples, digital control signals may be used for coordinating the enablement of the at least one receiver lane to function as the synthesized clock source and for coordinating the enablement of the other receiver lanes to perform BIST operations.

Abstract: Methods and systems for calibrating clock skew in a SerDes receiver. A method includes detecting a skew in a clock with respect to an edge of a reference clock, based on a value sampled by the clock and a value sampled by the reference clock at an edge of a data pattern, for a first Phase Interpolator (PI) code; determining a count of the skew from a de-serialized data word including outcome values obtained based on values sampled by the clock and values sampled by the reference clock at a predefined number of edges of the data pattern; obtaining a skew calibration code corresponding to the first PI code, from a binary variable obtained by accumulating an encoded variable to a previously generated binary variable; and calibrating the skew by performing a positive phase shift or a negative phase shift to the clock based on the skew calibration code.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: The present disclosure describes a telemetry redundant measurement avoidance protocol (TRMAP) that solves redundant data collection problems in telemetry systems. The TRMAP can operate in a non-supervised environment and/or in a distributed manner, and does not require a central controller to manage multiple collection agents in one or multiple telemetry systems. The TRMAP can also be an opt-in-based protocol that favors altruistic data sharing and reuse between collection agents. In these ways, the TRMAP provides freedom and collaboration among developers or other entities that desired telemetry data, while allowing non-compliant collection agents to coexist, if possible.

Abstract: A method, a computer system, and a computer program product for detection of unintended dependencies between hardware design signals from pseudo-random number generator (PRNG) taps is provided. Embodiments of the present invention may include identifying one or more tap points in a design as an execution sequence. Embodiments of the present invention may include sampling the tap points by propagating the tap points in the design with different delays. Embodiments of the present invention may include defining observation points to identify tap collisions based on the tap points. Embodiments of the present invention may include identifying tap collisions. Embodiments of the present invention may include identifying one or more sources of the tap collisions in the design. Embodiments of the present invention may include eliminating the one or more sources of uninteresting tap collisions out of the tap collisions and filtering one or more of the tap collisions.

Abstract: An information handling system includes a basic input/output system (BIOS) that performs a firmware boot operation. During the firmware boot operation, the BIOS determines whether a driver pack management controller setting is enabled within a baseboard management controller of the information handling system. In response to the driver pack management controller setting being enabled, the BIOS copies a binary utility from the baseboard management controller to a system memory, and creates an operating system specific platform binary table to point to the binary utility on the baseboard management controller. In response to the operating system being initialized, a processor invokes the binary utility, mounts a memory partition of the baseboard management controller as a virtual drive of the operating system, and executes the operating system specific binary stage under a fixed globally unique identifier to install a driver pack.

Abstract: An information handling system includes a basic input/output system (BIOS) that performs a firmware boot operation. During the firmware boot operation, the BIOS determines whether a driver pack management controller setting is enabled within a baseboard management controller of the information handling system. In response to the driver pack management controller setting being enabled, the BIOS copies a binary utility from the baseboard management controller to a system memory, and creates an operating system specific platform binary table to point to the binary utility on the baseboard management controller. In response to the operating system being initialized, a processor invokes the binary utility, mounts a memory partition of the baseboard management controller as a virtual drive of the operating system, and executes the operating system specific binary stage under a fixed globally unique identifier to install a driver pack.

Abstract: A technique for operating a data processing system includes determining, by an arbiter of a processing unit of the data processing system, whether an over-commit has occurred. In response to determining that the over-commit has occurred, the arbiter selects a broadcast command to be dropped based on a number of hops traversed through the data processing system by the broadcast command.

Abstract: According to one embodiment, a system includes a signaling connector comprising one or more wires. Each wire is capable of transmitting signaling between first and second components of an information handling system. A light-pipe is provided with the signaling connector. The light-pipe is capable of conveying light from one end of the signaling connector to another end of signaling connector so that the signaling connector can be traced.

Abstract: According to one embodiment, a system includes a signaling connector comprising one or more wires. Each wire is capable of transmitting signaling between first and second components of an information handling system. A light-pipe is provided with the signaling connector. The light-pipe is capable of conveying light from one end of the signaling connector to another end of signaling connector so that the signaling connector can be traced.

Abstract: A technique for operating a data processing system includes detecting that a processing unit within a first group of processing units in the data processing system has a hang condition. In response to detecting that the processing unit has a hang condition, a command issue rate for the first group of processing units is reduced. One or more other groups of processing units in the data processing system are notified that the first group of processing units has reduced the command issue rate for the first group of processing units. In response to the notifying, respective command issue rates of the other groups of processing units are reduced to reduce a number of commands received by the first group of processing units from the other groups of processing units.

Abstract: Method for controlling and detecting ammonium nitrate and/or ammonium nitrite poisoning within selective catalytic reduction (SCR) devices and systems incorporating the same are provided. Methods can include detecting a SCR inlet exhaust gas NO2:NOx ratio above a poisoning NOx flux threshold, detecting a SCR temperature below a poisoning temperature threshold, and determining SCR catalyst poisoning. Methods can further include performing a SCR catalyst cleaning strategy, wherein the SCR cleaning strategy comprises heating the SCR catalyst composition to a temperature above the poisoning temperature threshold. Cleaning strategies can including utilizing a heater, implementing a post-injection, after-injection, and/or auxiliary injection engine strategy wherein the engine is configured to supply exhaust gas to the SCR.