Patents by Inventor Praveen Shukla
Praveen Shukla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10410713Abstract: Aspects of the disclosed technology relate to techniques for modeling content-addressable memory in emulation and prototyping. A model for content-addressable memory comprises memory circuitry configured to store match results for various search keys. The match results are stored in the second memory circuitry during write operations. The model for content-addressable memory may further comprise additional memory circuitry configured to operate as a standard computer memory, performing read operations alone and write operations along with the memory circuitry.Type: GrantFiled: October 3, 2017Date of Patent: September 10, 2019Assignee: Mentor Graphics CorporationInventors: Charles W. Selvidge, Sanjay Gupta, Krishnamurthy Suresh, Praveen Shukla, Saurabh Gupta
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Patent number: 9990452Abstract: Aspects of the disclosed technology relate to techniques for corrupting memories in emulation. After a power domain in a circuit design being emulated in an emulator is powered down, a main memory model for a memory in the power domain is corrupted and a cache memory model for the memory is invalidated. The cache memory model is a hardware model in the emulator and the main memory model is a software model in a workstation coupled to the emulator. The cache memory model stores a subset of data that are stored in the main memory model. The combination of the main memory model and the cache memory model is used to model the memory.Type: GrantFiled: November 13, 2015Date of Patent: June 5, 2018Assignee: Mentor Graphics CorporationInventors: Krishnamurthy Suresh, Mukesh Gupta, Praveen Shukla, Sanjay Gupta
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Patent number: 9959379Abstract: Aspects of the disclosed technology relate to techniques of design implementation for FPGA prototyping. An initial FPGA-mapped netlist and a generic RTL design associated with the initial FPGA-mapped netlist are generated based on an original RTL (register-transfer level) design for a circuit design and optionally on verification-related features. Based on the initial FPGA-mapped netlist, the circuit design is partitioned into design partitions for implementing the circuit design across a plurality of FPGA chips. Final FPGA-mapped netlists are then generated based on the design partitions represented by the generic RTL design or by a combination of the generic RTL design and the initial FPGA-mapped netlist.Type: GrantFiled: July 11, 2016Date of Patent: May 1, 2018Assignee: Mentor Graphics CorporationInventors: Sanjay Gupta, Praveen Shukla
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Publication number: 20170140084Abstract: Aspects of the disclosed technology relate to techniques for corrupting memories in emulation. After a power domain in a circuit design being emulated in an emulator is powered down, a main memory model for a memory in the power domain is corrupted and a cache memory model for the memory is invalidated. The cache memory model is a hardware model in the emulator and the main memory model is a software model in a workstation coupled to the emulator. The cache memory model stores a subset of data that are stored in the main memory model. The combination of the main memory model and the cache memory model is used to model the memory.Type: ApplicationFiled: November 13, 2015Publication date: May 18, 2017Inventors: Krishnamurthy Suresh, Mukesh Gupta, Praveen Shukla, Sanjay Gupta
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Publication number: 20170103156Abstract: Aspects of the disclosed technology relate to techniques of design implementation for FPGA prototyping. An initial FPGA-mapped netlist and a generic RTL design associated with the initial FPGA-mapped netlist are generated based on an original RTL (register-transfer level) design for a circuit design and optionally on verification-related features. Based on the initial FPGA-mapped netlist, the circuit design is partitioned into design partitions for implementing the circuit design across a plurality of FPGA chips. Final FPGA-mapped netlists are then generated based on the design partitions represented by the generic RTL design or by a combination of the generic RTL design and the initial FPGA-mapped netlist.Type: ApplicationFiled: July 11, 2016Publication date: April 13, 2017Inventors: Sanjay Gupta, Praveen Shukla
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Patent number: 9305126Abstract: Aspects of the invention relate to techniques for using retiming to reduce circuit switching activity. Switching activity values at output ports of circuit elements of a circuit design are first computed based on switching activity values at input ports of the circuit elements and scaling factors associated with the circuit elements. Based on the switching activity values at the output ports of the circuit elements, one or more regions of the circuit design for retiming are identified. Retiming location information is then determined for the one or more regions. Finally, the identified one or more regions are then retimed to reduce switching activity based on the retiming location information.Type: GrantFiled: March 21, 2014Date of Patent: April 5, 2016Assignee: Mentor Graphics CorporationInventors: Charles W. Selvidge, Sanjay Gupta, Praveen Shukla, Saurabh Gupta, Jeffrey Evans
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Publication number: 20150269295Abstract: Aspects of the invention relate to techniques for using retiming to reduce circuit switching activity. Switching activity values at output ports of circuit elements of a circuit design are first computed based on switching activity values at input ports of the circuit elements and scaling factors associated with the circuit elements. Based on the switching activity values at the output ports of the circuit elements, one or more regions of the circuit design for retiming are identified. Retiming location information is then determined for the one or more regions. Finally, the identified one or more regions are then retimed to reduce switching activity based on the retiming location information.Type: ApplicationFiled: March 21, 2014Publication date: September 24, 2015Applicant: Mentor Graphics CorporationInventors: Charles W. Selvidge, Sanjay Gupta, Praveen Shukla, Saurabh Gupta, Jeffrey Evans
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Publication number: 20150018579Abstract: The 5? and 3?-thiol modified oligonucleotides are attractive tools with a vast number of potential applications in the field of nucleic acid chemistry. There is a strong interest in developing new disulfide compounds or to optimize synthesis of existing disulfide modifiers, which are efficient in generating the 3?- or 5?-end reactive thiol group. Various synthetic protocols have been employed to synthesize pure 3-((3-(bis(4-dimethoxytrityl)propyl)di-sulfanyl)propyl 2-cyanoethyl diisopropylphosphoramidite (compound 2) starting from 3-(dimethoxytrityl)propyl)disulfanyl)pro-pan-1-ol, (compound 1). Herein, we describe an efficient, reproducible synthetic and purification protocol for target compound 2 from the compound 1. It is noteworthy that our reaction conditions were reproducible even at multi-gram scale (27 g) with a purity level as achieved in a small scale.Type: ApplicationFiled: February 22, 2012Publication date: January 15, 2015Inventors: Suresh C. Srivastava, Santhosh K. Thatikonda, Praveen Shukla, Sant Kumar Srivastav
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Patent number: 8516411Abstract: Techniques and tool for selecting compilation parameter values for compiling a first description of a circuit design, such as a register transfer language description, into a second description of the circuit design, such as a model description for implementation with an emulator are provided. According to various examples of the invention, a compilation tool “elaborates” the first description of the circuit design into a third description for the circuit design. Typically, the third description or “elaboration” will cross one or more hierarchical boundaries represented in the first description of the circuit design, so that the elaboration will represent at least a portion of two or more hierarchical modules in the first description design according to a non-hierarchical or “flat” manner. Also, with some implementations of the invention, the elaboration may include only a simple representation of a corresponding portion of the circuit design.Type: GrantFiled: January 31, 2011Date of Patent: August 20, 2013Assignee: Mentor Graphics CorporationInventors: Sanjay Gupta, Charles W. Selvidge, Praveen Shukla
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Publication number: 20120180011Abstract: Techniques and tool for selecting compilation parameter values for compiling a first description of a circuit design, such as a register transfer language description, into a second description of the design, such as a model description for implementation with an emulator are provided. According to various examples of the invention, a compilation tool “elaborates” a first description of a circuit design into a third description for a circuit design. Typically, the third description or “elaboration” will cross one or more hierarchical boundaries represented in the first description of the design, so that the elaboration will represent at least a portion of two or more hierarchical modules in the first description design according to a non-hierarchical or “flat” manner. Also, with some implementations of the invention, the elaboration may include only a simple representation of the corresponding portion of the circuit design.Type: ApplicationFiled: January 31, 2011Publication date: July 12, 2012Inventors: Sanjay Gupta, Charles W. Selvidge, Praveen Shukla