Abstract: A single-wire bus (SuBUS) apparatus is provided. The SuBUS apparatus includes a master circuit coupled to a slave circuit(s) by a SuBUS. The master circuit can enable or suspend a SuBUS telegram communication over the SuBUS. When the master circuit suspends the SuBUS telegram communication over the SuBUS, the slave circuit(s) may draw a charging current via the SuBUS to perform a defined slave operation. Notably, the master circuit may not have knowledge about exact completion time of the defined slave operation and thus may be unable to resume the SuBUS telegram communication in a timely manner. The slave circuit(s) can be configured to generate a predefined interruption pulse sequence to cause the master circuit to resume the SuBUS telegram communication over the SuBUS. As such, it may be possible for the master circuit to quickly resume the SuBUS telegram communication, thus helping to improve throughput of the SuBUS.

Abstract: A single-wire bus (SuBUS) apparatus is provided. The SuBUS apparatus includes a master circuit coupled to a slave circuit(s) by a SuBUS. The master circuit can enable or suspend a SuBUS telegram communication over the SuBUS. When the master circuit suspends the SuBUS telegram communication over the SuBUS, the slave circuit(s) may draw a charging current via the SuBUS to perform a defined slave operation. Notably, the master circuit may not have knowledge about exact completion time of the defined slave operation and thus may be unable to resume the SuBUS telegram communication in a timely manner. The slave circuit(s) can be configured to generate a predefined interruption pulse sequence to cause the master circuit to resume the SuBUS telegram communication over the SuBUS. As such, it may be possible for the master circuit to quickly resume the SuBUS telegram communication, thus helping to improve throughput of the SuBUS.

Abstract: This disclosure relates generally to digital bus interfaces. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry that includes a power converter configured to convert the input data signal from the master bus controller into a supply voltage. The power conversion circuitry is also configured to generate a charge current from the input data signal. In this manner, the charge current can be used to regulate the supply voltage and maintain the appropriate charge.

Abstract: The present disclosure relates to a bus interface system including a bus line, master integrated circuitry (IC), and slave IC. The master IC is coupled to the bus line and configured to transmit the data signal to the slave IC through the bus line. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor, which is configured to store power from the data signal and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.

Abstract: An integrated circuit (IC) including a first power-on reset (POR) circuit and a second POR circuit is disclosed. The first POR circuit is configured to enable the second POR circuit when a supply voltage initially exceeds a first threshold voltage as the supply voltage is being applied to the IC. The second POR circuit is configured to activate a first section of circuitry when the second POR circuit is enabled by the first POR circuit and the supply voltage initially exceeds a second threshold voltage as the supply voltage is being applied to the IC. Since a POR threshold voltage can affect current drain and/or operational functions of an IC, having the first POR circuit configured to enable the second POR circuit and having the second POR circuit configured to activate the first section of the main circuitry allows the IC to operate properly while reducing current drain.

Abstract: The present disclosure relates to a bus interface system including a bus line, master integrated circuitry (IC), and slave IC. The master IC is coupled to the bus line and configured to transmit the data signal to the slave IC through the bus line. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor, which is configured to store power from the data signal and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.

Abstract: An integrated circuit (IC) including a first power-on reset (POR) circuit and a second POR circuit is disclosed. The first POR circuit is configured to enable the second POR circuit when a supply voltage initially exceeds a first threshold voltage as the supply voltage is being applied to the IC. The second POR circuit is configured to activate a first section of circuitry when the second POR circuit is enabled by the first POR circuit and the supply voltage initially exceeds a second threshold voltage as the supply voltage is being applied to the IC. Since a POR threshold voltage can affect current drain and/or operational functions of an IC, having the first POR circuit configured to enable the second POR circuit and having the second POR circuit configured to activate the first section of the main circuitry allows the IC to operate properly while reducing current drain.

Abstract: Radio frequency (RF) amplification devices are disclosed along with methods of providing power to an RF signal. In one embodiment, an RF amplification device includes an RF amplification circuit and a voltage regulation circuit. The RF amplification circuit includes a plurality of RF amplifier stages coupled in cascade. The voltage regulation circuit is coupled to provide a regulated voltage to a driver RF amplifier stage. The voltage regulation circuit is configured to generate the regulated voltage so that the maximum output power of the RF amplification circuit is provided approximately at a first power level while the supply voltage is above a threshold voltage level. The first power level should be within the physical capabilities of the RF amplification circuit, and thus, the RF amplification circuit is prevented from being damaged once the supply voltage is above the threshold voltage level.

Abstract: This disclosure relates generally to digital bus interfaces. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry that includes a power converter configured to convert the input data signal from the master bus controller into a supply voltage. The power conversion circuitry is also configured to generate a charge current from the input data signal. In this manner, the charge current can be used to regulate the supply voltage and maintain the appropriate charge.

Abstract: An RF electronics module includes a grounding plate, a non-conductive substrate, a number of conductive vias, RF PA circuitry, and RF power detection circuitry. The non-conductive substrate is over the grounding plate. The conductive vias extend parallel to one another from a surface of the non-conductive substrate opposite the grounding plate through the non-conductive substrate to the grounding plate. The RF PA circuitry is coupled to the grounding plate through a first one of the conductive vias. The RF power detection circuitry is coupled to a second one of the conductive vias and configured to measure a signal induced in the second one of the conductive vias due to electromagnetic coupling with the first one of conductive vias. The first one of the conductive vias is adjacent to the second one of the conductive vias.

Abstract: The present disclosure provides a power amplifier controller for starting up, operating, and shutting down a power amplifier. The power amplifier controller includes current sense amplifier circuitry adapted to monitor a main current of the power amplifier. A bias generator is also included and adapted to provide a predetermined standby bias voltage and an operational bias voltage based upon a main current level sensed by the current sense amplifier circuitry. The power amplifier controller further includes a sequencer adapted to control startup and shutdown sequences of the power amplifier. In at least one embodiment, the power amplifier is a gallium nitride (GaN) device, and the main current level sensed is a drain current of the GaN device. Moreover, the bias generator is a gate bias generator provided that the power amplifier is a field effect transistor (FET) device.

Abstract: An RF electronics module includes a grounding plate, a non-conductive substrate, a number of conductive vias, RF PA circuitry, and RF power detection circuitry. The non-conductive substrate is over the grounding plate. The conductive vias extend parallel to one another from a surface of the non-conductive substrate opposite the grounding plate through the non-conductive substrate to the grounding plate. The RF PA circuitry is coupled to the grounding plate through a first one of the conductive vias. The RF power detection circuitry is coupled to a second one of the conductive vias and configured to measure a signal induced in the second one of the conductive vias due to electromagnetic coupling with the first one of conductive vias. The first one of the conductive vias is adjacent to the second one of the conductive vias.

Abstract: Radio frequency (RF) amplification devices are disclosed along with methods of providing power to an RF signal. In one embodiment, an RF amplification device includes an RF amplification circuit and a voltage regulation circuit. The RF amplification circuit includes a plurality of RF amplifier stages coupled in cascade. The voltage regulation circuit is coupled to provide a regulated voltage to a driver RF amplifier stage. The voltage regulation circuit is configured to generate the regulated voltage so that the maximum output power of the RF amplification circuit is provided approximately at a first power level while the supply voltage is above a threshold voltage level. The first power level should be within the physical capabilities of the RF amplification circuit, and thus, the RF amplification circuit is prevented from being damaged once the supply voltage is above the threshold voltage level.

Abstract: This disclosure relates to radio frequency (RF) amplification devices and methods for amplifying an RF input signal. To set the quiescent operating level of the RF output signal, a bias signal to be applied to the RF input signal is received prior to amplifying the RF input signal. The bias signal is amplified to generate the RF output signal at the quiescent operating level and a feedback signal is received that is indicative of the quiescent operating level of the RF output signal. Prior to amplifying the RF input signal, the bias signal level of the bias signal is adjusted such that the quiescent operating level is set to a reference signal level based on the feedback signal level. This allows for adjustments to be made to the quiescent operating level and maintain the quiescent operating level at a desired value.

Abstract: A differential voltage controlled current source generating one or more output currents is based upon a single external resistor. The differential voltage controlled current source may generate an output current that is proportional to a received differential voltage and a bias current with the use of a single external resistor. The technique may be used to generate multiple accurate and process independent current sources. The current sources may be a zero temperature coefficient (ZTC) current, a proportional to absolute temperature (PTAT) current, or an inversely proportional to absolute temperature (NTAT) current. The output of the current sources may be inversely proportional to the resistance of the external resistor.

Abstract: The present disclosure provides a power amplifier controller for starting up, operating, and shutting down a power amplifier. The power amplifier controller includes current sense amplifier circuitry adapted to monitor a main current of the power amplifier. A bias generator is also included and adapted to provide a predetermined standby bias voltage and an operational bias voltage based upon a main current level sensed by the current sense amplifier circuitry. The power amplifier controller further includes a sequencer adapted to control startup and shutdown sequences of the power amplifier. In at least one embodiment, the power amplifier is a gallium nitride (GaN) device, and the main current level sensed is a drain current of the GaN device. Moreover, the bias generator is a gate bias generator provided that the power amplifier is a field effect transistor (FET) device.

Abstract: An exemplary embodiment of an analog multiplier may include a voltage controlled resistance circuit, a first transistor and a second transistor, where the resistance of the voltage controlled resistance circuit is based upon a first input voltage. The current passing through the voltage controlled resistance circuit is based upon a second input voltage. The first transistor and the second transistor form a current mirror to mirror the current passing through the voltage controlled resistance circuit to provide a power supply control current to a wideband code division multiple access radio frequency power amplifier.

Abstract: An exemplary embodiment of an analog multiplier may include a voltage controlled resistance circuit, a first transistor and a second transistor, where the resistance of the voltage controlled resistance circuit is based upon a difference between a supply voltage and a first input voltage and a constant current supply. The current passing through the voltage controlled resistance circuit is based upon a difference between the voltage supply and a second input voltage. The first transistor may be configured to mirror the current passing through the voltage controlled resistance circuit.

Abstract: A charge-pump circuit includes at least one flying capacitor stage having a capacitor with a first terminal selectively coupled between a negative voltage input through a first electronic switch and a negative voltage output through a second electronic switch. A second terminal of the capacitor is selectively coupled between a fixed voltage node through a third electronic switch and an error signal input through a fourth electronic switch. A positive voltage source is coupled to the negative voltage output through a feedback network. A feedback amplifier having an error signal output, a reference voltage input, and a feedback input is coupled to the feedback network. A switch controller having a first clock output drives the first electronic switch and the third electronic switch, while a second clock output drives the second electronic switch and the fourth electronic switch.

Abstract: A current digital-to-analog converter (DAC) is disclosed. The current DAC includes a current reference circuit coupled between a voltage source terminal and a voltage node, wherein the current reference circuit includes a feedback node. A switchable resistor network is communicably coupled to the feedback node of the current reference circuit via a first feedback network that is adapted to equalize a first voltage across the switchable resistor network voltage with a second voltage between the feedback node and the voltage node. A current mirror includes an output node communicably coupled to the switchable resistor network via a second feedback network that is adapted to equalize an output current that flows from the output node with an input current that flows into the switchable resistor network.