Patents by Inventor Pravesh Gupta
Pravesh Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250110773Abstract: The disclosed device includes a heterogeneous processor architecture having heterogeneous processors, and a control circuit that can assign, in response to an interrupt, the interrupt to one of the heterogenous processors that is selected based on power efficiency. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Advanced Micro Devices, Inc.Inventors: Pravesh Gupta, Benjamin Tsien
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Patent number: 12045182Abstract: A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.Type: GrantFiled: April 11, 2023Date of Patent: July 23, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Eric Christopher Morton, Pravesh Gupta, Bryan P Broussard, Li Ou
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Patent number: 12001265Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.Type: GrantFiled: September 23, 2021Date of Patent: June 4, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Alexander J. Branover, Christopher T. Weaver, Indrani Paul, Mihir Shaileshbhai Doctor, John P. Petry, Stephen V. Kosonocky, Thomas J. Gibney, Jose G. Cruz, Pravesh Gupta, Chintan S. Patel
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Patent number: 11947476Abstract: Methods and systems are disclosed for cross-chiplet performance data streaming. Techniques disclosed include accumulating, by a subservient chiplet, event data associated with an event indicative of a performance aspect of the subservient chiplet; sending, by the subservient chiplet, the event data over a chiplet bus to a master chiplet; and adding, by the master chiplet, the received event data to an event record, the event record containing previously received, from the subservient chiplet over the chiplet bus, event data associated with the event.Type: GrantFiled: March 31, 2022Date of Patent: April 2, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Bryan Broussard, Pravesh Gupta, Benjamin Tsien, Vydhyanathan Kalyanasundharam
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Publication number: 20230315657Abstract: Methods and systems are disclosed for cross-chiplet performance data streaming. Techniques disclosed include accumulating, by a subservient chiplet, event data associated with an event indicative of a performance aspect of the subservient chiplet; sending, by the subservient chiplet, the event data over a chiplet bus to a master chiplet; and adding, by the master chiplet, the received event data to an event record, the event record containing previously received, from the subservient chiplet over the chiplet bus, event data associated with the event.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Bryan Broussard, Pravesh Gupta, Benjamin Tsien, Vydhyanathan Kalyanasundharam
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Patent number: 11734151Abstract: An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal. Responsive to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than the reference clock, the first circuit adjusts the frequency of the adjustable clock to a frequency higher than the lower frequency, and then receives an elapsed time associated with the non-operational power state and starts the timer using an adjusted timer value.Type: GrantFiled: June 24, 2021Date of Patent: August 22, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Pravesh Gupta
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Patent number: 11675718Abstract: A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.Type: GrantFiled: March 26, 2021Date of Patent: June 13, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Eric Christopher Morton, Pravesh Gupta, Bryan P Broussard, Li Ou
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Publication number: 20230090126Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Alexander J. Branover, Christopher T. Weaver, Indrani Paul, Mihir Shaileshbhai Doctor, John P. Petry, Stephen V. Kosonocky, Thomas J. Gibney, Jose G. Cruz, Pravesh Gupta, Chintan S. Patel
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Publication number: 20220413984Abstract: An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal. Responsive to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than the reference clock, the first circuit adjusts the frequency of the adjustable clock to a frequency higher than the lower frequency, and then receives an elapsed time associated with the non-operational power state and starts the timer using an adjusted timer value.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Benjamin Tsien, Pravesh Gupta
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Publication number: 20220309013Abstract: A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Inventors: Eric Christopher Morton, Pravesh Gupta, Bryan P Broussard, Li Ou
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Patent number: 11341069Abstract: A method of operating a processing unit includes storing a first copy of a first interrupt control value in a cache device of the processing unit, receiving from an interrupt controller a first interrupt message transmitted via an interconnect fabric, where the first interrupt message includes a second copy of the first interrupt control value, and if the first copy matches the second copy, servicing an interrupt specified in the first interrupt message.Type: GrantFiled: October 12, 2020Date of Patent: May 24, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Bryan P Broussard, Paul Moyer, Eric Christopher Morton, Pravesh Gupta
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Publication number: 20220114123Abstract: A method of operating a processing unit includes storing a first copy of a first interrupt control value in a cache device of the processing unit, receiving from an interrupt controller a first interrupt message transmitted via an interconnect fabric, where the first interrupt message includes a second copy of the first interrupt control value, and if the first copy matches the second copy, servicing an interrupt specified in the first interrupt message.Type: ApplicationFiled: October 12, 2020Publication date: April 14, 2022Inventors: Bryan P Broussard, Paul Moyer, Eric Christopher Morton, Pravesh Gupta