Abstract: A method and system are directed to generating on-chip bitstreams on reconfigurable hardware. The system comprises a built-in bitstream initialization (BIBI) module configured to generate one or more bitstreams on a semiconductor device. The BIBI module comprising a sequence generator configured to generate a sequence of values for each of the one or more bitstreams, a masking module configured to convert the sequence of values to a given precision of bits, an encryption module configured to apply an encryption scheme to the sequence of values, and an error correction module configured to apply error correction on the sequence of values, wherein the one or more bitstreams are transmitted to a routing network configured to map the one or more bitstreams to input positions of one or more compute blocks.

Abstract: Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality.

Abstract: Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality.