Patents by Inventor Pravin Pathak
Pravin Pathak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260064462Abstract: In an embodiment, a processor may include multiple processing engines and multiple hardware queue manager (HQM) devices. Each HQM device is to queue data requests for a different subset of the plurality of processing engines. At least one processing engine is to execute a first set of instructions to: detect a first enqueue instruction to enqueue data in a first HQM device of the plurality of HQM devices; in response to a detection of the first enqueue instruction, perform a look-up of the first HQM device in a data structure to determine a recommended port for the first HQM device; and transmit the first enqueue instruction using the recommended port for the first HQM device.Type: ApplicationFiled: September 27, 2022Publication date: March 5, 2026Applicant: Intel CorporationInventors: Pushpendra Kumar, Amruta Misra, Niall McDonnell, Ambalavanar Arulambalam, Ximing Chen, Paul Beatty, Pravin Pathak
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Publication number: 20260010402Abstract: Examples described herein relate to a work scheduler that includes at least one processor and at least one queue. In some examples, the work scheduler receives a request to allocate a region of memory and based on availability of a memory segment associated with a central cache to satisfy the request to allocate a region of memory, provide a memory allocation using an available memory segment entry associated with the central cache from the at least one queue. In some examples, the work scheduler assigns a workload to a processor and controls when to pre-fetch content relevant to the workload to store in a cache or memory accessible to the processor based on a position of the workload in a work queue associated with the processor.Type: ApplicationFiled: September 15, 2025Publication date: January 8, 2026Inventors: Yipeng WANG, Ren WANG, Tsung-Yuan C. TAI, Yifan YUAN, Pravin PATHAK, Sundar VEDANTHAM, Chris MACNAMARA
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Patent number: 12452186Abstract: Methods and apparatus to assign and check anti-replay sequence numbers. In one embodiment, a method includes assigning, by circuitry, sequence numbers to packets of traffic flows, wherein a first sequence number is assigned to a first packet based on a determination that the first packet is within a first traffic flow mapped to a first secure channel, and wherein the first sequence number is within a set of sequence numbers allocated to the first secure channel and maintained by the circuitry. The method continues with allocating the packets of traffic flows to be processed among a plurality of processor cores and processing the packets of traffic flows by the plurality of processor cores.Type: GrantFiled: December 16, 2021Date of Patent: October 21, 2025Assignee: Intel CorporationInventors: Niall McDonnell, Pravin Pathak, Rahul Shah, Declan Doherty
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Patent number: 12443443Abstract: Examples described herein relate to a work scheduler that includes at least one processor and at least one queue. In some examples, the work scheduler receives a request to allocate a region of memory and based on availability of a memory segment associated with a central cache to satisfy the request to allocate a region of memory, provide a memory allocation using an available memory segment entry associated with the central cache from the at least one queue. In some examples, the work scheduler assigns a workload to a processor and controls when to pre-fetch content relevant to the workload to store in a cache or memory accessible to the processor based on a position of the workload in a work queue associated with the processor.Type: GrantFiled: February 24, 2020Date of Patent: October 14, 2025Assignee: SK Hynix NAND Product Solutions Corp.Inventors: Yipeng Wang, Ren Wang, Tsung-Yuan C. Tai, Yifan Yuan, Pravin Pathak, Sundar Vedantham, Chris MacNamara
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Patent number: 12210632Abstract: Examples described herein relate to a manner of provide a time of life of data. In some examples, data and control parameters are received from a data source. The data can be encrypted and stored. In addition, at least a portion of the control parameters can be stored into a distributed ledger. In some examples, the portion of the control parameters include an indicator of expiration time of the data. In some examples, a data header for the data is generated, where the data header includes an indication that the data is subject to a limited life span and a data identifier. The data header can be accessed with a request to access the encrypted data. In some examples, a request to determine if the data is valid and accessible is provided to a node of the distributed ledger and an indication of whether the data is valid and accessible is received from a node in the distributed ledger.Type: GrantFiled: October 28, 2020Date of Patent: January 28, 2025Assignee: Intel CorporationInventors: Sundar Vedantham, Bin Lin, Pravin Pathak, Ximing Chen, Chris MacNamara
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Publication number: 20230401109Abstract: Examples described herein relate to a load balancer that is configured to selectively perform ordering of requests from the one or more cores, allocate the requests into queue elements prior to allocation to one or more receiver cores of the one or more cores to process the requests, and perform two or more operations of: adjust a number of queues associated with a core of the one or more cores by changing a number of consumer queues (CQs) allocated to a single domain, adjust a number of target cores in a group of target cores to be load balanced, and order memory space writes from multiple caching agents (CAs).Type: ApplicationFiled: August 24, 2023Publication date: December 14, 2023Inventors: Niall D. MCDONNELL, Ambalavanar ARULAMBALAM, Te Khac MA, Surekha PERI, Pravin PATHAK, James CLEE, An YAN, Steven POLLOCK, Bruce RICHARDSON, Vijaya Bhaskar KOMMINENI, Abhinandan GUJJAR
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Publication number: 20230198912Abstract: Methods and apparatus to assign and check anti-replay sequence numbers. In one embodiment, a method includes assigning, by circuitry, sequence numbers to packets of traffic flows, wherein a first sequence number is assigned to a first packet based on a determination that the first packet is within a first traffic flow mapped to a first secure channel, and wherein the first sequence number is within a set of sequence numbers allocated to the first secure channel and maintained by the circuitry. The method continues with allocating the packets of traffic flows to be processed among a plurality of processor cores and processing the packets of traffic flows by the plurality of processor cores.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Inventors: Niall MCDONNELL, Pravin PATHAK, Rahul SHAH, Declan DOHERTY
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Publication number: 20220107838Abstract: Examples relate to an apparatus, device, method, and computer program for processing a sequence of units of data, and of a computer program comprising such an apparatus or device.Type: ApplicationFiled: December 14, 2021Publication date: April 7, 2022Inventors: Niall MCDONNELL, Bruce RICHARDSON, Rahul SHAH, Pravin PATHAK, Rashmi SHETTY
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Publication number: 20210049285Abstract: Examples described herein relate to a manner of provide a time of life of data. In some examples, data and control parameters are received from a data source. The data can be encrypted and stored. In addition, at least a portion of the control parameters can be stored into a distributed ledger. In some examples, the portion of the control parameters include an indicator of expiration time of the data. In some examples, a data header for the data is generated, where the data header includes an indication that the data is subject to a limited life span and a data identifier. The data header can be accessed with a request to access the encrypted data. In some examples, a request to determine if the data is valid and accessible is provided to a node of the distributed ledger and an indication of whether the data is valid and accessible is received from a node in the distributed ledger.Type: ApplicationFiled: October 28, 2020Publication date: February 18, 2021Inventors: Sundar VEDANTHAM, Bin LIN, Pravin PATHAK, Ximing CHEN, Chris MACNAMARA
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Publication number: 20200192715Abstract: Examples described herein relate to a work scheduler that includes at least one processor and at least one queue. In some examples, the work scheduler receives a request to allocate a region of memory and based on availability of a memory segment associated with a central cache to satisfy the request to allocate a region of memory, provide a memory allocation using an available memory segment entry associated with the central cache from the at least one queue. In some examples, the work scheduler assigns a workload to a processor and controls when to pre-fetch content relevant to the workload to store in a cache or memory accessible to the processor based on a position of the workload in a work queue associated with the processor.Type: ApplicationFiled: February 24, 2020Publication date: June 18, 2020Inventors: Yipeng WANG, Ren WANG, Tsung-Yuan C. TAI, Yifan YUAN, Pravin PATHAK, Sundar VEDANTHAM, Chris MACNAMARA
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Publication number: 20190253357Abstract: A computing platform includes a classifier to classify a packet and assign a processing load weight to the packet based at least in part on the packet classification; and a load balancer coupled to the classifier to compute a total processing load weight of a queue of a packet processing system and assign the packet to a queue with a lowest total processing load weight.Type: ApplicationFiled: October 15, 2018Publication date: August 15, 2019Inventors: Pravin PATHAK, Sundar VEDANTHAM, David SONNIER
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Publication number: 20060013210Abstract: A method and apparatus are disclosed for per-service flow protection and restoration of data in one or more packet networks. The disclosed protection and restoration techniques allow traffic to be prioritized and protected from the aggregate level down to a micro-flow level. Thus, protection can be limited to those services that are fault sensitive. Protected data is duplicated over a primary path and one or more backup data paths. Following a link failure, protected data can be quickly and efficiently restored without significant service interruption. A received packet is classified at each end point based on information in a header portion of the packet, using one or more rules that determine whether the received packet should be protected. At an ingress node, if the packet classification determines that the received packet should be protected, then the received packet is transmitted on at least two paths.Type: ApplicationFiled: June 18, 2004Publication date: January 19, 2006Inventors: Mark Bordogna, Christopher Hamilton, Deepak Kataria, Pravin Pathak, Mark Simkins