Patents by Inventor Prayag Bhanubhai Patel
Prayag Bhanubhai Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9673786Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.Type: GrantFiled: April 12, 2013Date of Patent: June 6, 2017Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Jay Madhukar Shah, Martin Saint-Laurent, Peeyush Kumar Parkar, Sachin Bapat, Ramaprasath Vilangudipitchai, Mohamed Hassan Abu-Rahma, Prayag Bhanubhai Patel
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Patent number: 9178496Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.Type: GrantFiled: January 26, 2015Date of Patent: November 3, 2015Assignee: QUALCOMM IncorporatedInventors: Ramaprasath Vilangudipitchai, Prayag Bhanubhai Patel
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Patent number: 9093995Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.Type: GrantFiled: May 29, 2013Date of Patent: July 28, 2015Assignee: QUALCOMM IncorporatedInventors: Kashyap Ramachandra Bellur, HariKrishna Chintarlapalli Reddy, Martin Saint-Laurent, Pratyush Kamal, Prayag Bhanubhai Patel, Esin Terzioglu
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Publication number: 20150130524Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.Type: ApplicationFiled: January 26, 2015Publication date: May 14, 2015Inventors: Ramaprasath Vilangudipitchai, Prayag Bhanubhai Patel
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Patent number: 8975934Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.Type: GrantFiled: March 6, 2013Date of Patent: March 10, 2015Assignee: QUALCOMM IncorporatedInventors: Ramaprasath Vilangudipitchai, Prayag Bhanubhai Patel
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Publication number: 20140354338Abstract: A circuit includes a pulsed-latch circuit. The pulsed-latch circuit includes a first plurality of transistors. One or more of the first plurality of transistors is length-of-diffusion (LOD) protected.Type: ApplicationFiled: May 29, 2013Publication date: December 4, 2014Inventors: Kashyap Ramachandra Bellur, HariKrishna Chintarlapalli Reddy, Martin Saint-Laurent, Pratyush Kamal, Prayag Bhanubhai Patel, Esin Terzioglu
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Publication number: 20140306735Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.Type: ApplicationFiled: April 12, 2013Publication date: October 16, 2014Applicant: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Jay Madhukar Shah, Martin Saint-Laurent, Peeyush Kumar Parkar, Sachin Bapat, Ramaprasath Vilangudipitchai, Mohamed Hassan Abu-Rahma, Prayag Bhanubhai Patel
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Patent number: 8836040Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.Type: GrantFiled: November 7, 2012Date of Patent: September 16, 2014Assignee: QUALCOMM IncorporatedInventors: Pratyush Kamal, Esin Terzioglu, Foua Vang, Prayag Bhanubhai Patel, Giridhar Nallapati, Animesh Datta
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Publication number: 20140253197Abstract: A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Applicant: QUALCOMM IncorporatedInventors: Ramaprasath Vilangudipitchai, Prayag Bhanubhai Patel
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Publication number: 20140124868Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: QUALCOMM IncorporatedInventors: Pratyush Kamal, Esin Terzioglu, Foua Vang, Prayag Bhanubhai Patel, Giridhar Nallapati, Animesh Datta
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Patent number: 7352694Abstract: A system and method are provided for tolerating data line faults in a packet communications switch fabric. The method comprises: accepting information packets including a plurality of cells, at a plurality of ingress port card ports, the plurality of information packets addressing a plurality of egress port card ports; selectively connecting port card ports to port card backplane data links; selectively connecting port card backplane data links and crossbars; sensing a connection fault in a backplane data link; in response to sensing the fault, reselecting connections between the port card ports and the port card backplane data links; in response to reselecting connections between the port card ports and the port card backplane data links, serially transferring packets through the port cards; serially transferring packets through the crossbars to the egress port cards; and, suspending use of the faulty connection.Type: GrantFiled: February 24, 2003Date of Patent: April 1, 2008Assignee: Applied Micro Circuits CorporationInventors: Philip Michael Clovis, Eli James Aubrey Fernald, John David Huber, Kirk Alvin Miller, Sushil Kumar Singh, Prayag Bhanubhai Patel, Kenneth Yi Yun, George Beshara Bendak
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Patent number: 7298754Abstract: A system and method are provided for configuring interface bandwidths in a packet communications switch fabric. The method comprises: interfacing data links with a first plurality of traffic managers (TMs); differentiating port card interface ports into a first plurality of subchannels associated with the first plurality of TMs; and, communicating packets information with the TMs at a first plurality of data rates corresponding to the first plurality of subchannels. More specifically, differentiating port card interface ports into a first plurality of subchannels associated with the first plurality of TMs includes: differentiating a second plurality of ingress data links into a third plurality of ingress subchannels associated with a third plurality of ingress traffic managers (iTMs); and, differentiating a fourth plurality of egress data links into a fifth plurality of egress subchannels associated with a fifth plurality of egress TMs (eTMs).Type: GrantFiled: March 31, 2003Date of Patent: November 20, 2007Assignee: Applied Micro Circuits CorporationInventors: Kirk Alvin Miller, Prayag Bhanubhai Patel, George Beshara Bendak, Kenneth Yi Yun, Sushil Kumar Singh, Ayoob Eusoof Dooply, Michael John Hellmer
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Patent number: 7298756Abstract: A system and method are provided for controlling packet header information in a packet communications switch fabric. The method comprises: programming the cell header overhead (OH) field definitions; accepting a packet including a plurality of cells and corresponding cell headers, each cell header including a plurality of overhead fields; defining the cell header OH fields; and, transmitting the packet. Defining the cell header OH fields includes defining cell header OH field location, position, meaning, structure, and length. In other aspects, the method comprises redefining the cell header overhead fields, once they are accepted. For example, the OH field information can be modified, relocated, or an OH field can be added to the cell header. In yet other aspects, the OH field information can be extracted and/or reformatted.Type: GrantFiled: March 31, 2003Date of Patent: November 20, 2007Assignee: Applied Micro Circuits CorporationInventors: Kirk Alvin Miller, Prayag Bhanubhai Patel, Peter John Holzer, John Calvin Leung, George Beshara Bendak, Jim Lew
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Patent number: 7221652Abstract: A system and method are provided for tolerating data line faults in a packet communications network. The method comprises: serially transmitting information packets from at least one traffic manager (TM); at a switch fabric, accepting information packets at a plurality of ingress ports, the information packets addressing destination port card egress ports; selectively connecting port card ingress ports to port card egress ports; serially supplying information packets from a plurality of port card egress ports; sensing a connection fault between the switch fabric and the TM; and, in response to sensing the fault, reselecting connections between the switch fabric port card ports and the TM. Some aspects comprise: an ingress memory subsystem (iMS) receiving cells on an ingress port exceeding an error threshold. Then, reselecting connections between the port card ports and the TM includes the iMS sending a message to the iTM identifying the faulty ingress connection.Type: GrantFiled: March 3, 2003Date of Patent: May 22, 2007Assignee: Applied Micro Circuits CorporationInventors: Sushil Kumar Singh, Kenneth Yi Yun, Jianfeng Shi, Eli James Aubrey Fernald, Kirk Alvin Miller, Prayag Bhanubhai Patel, Ayoob Eusoof Dooply, George Beshara Bendak