Patents by Inventor Prayag Patel

Prayag Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Logic device and method supporting scan test
    Patent number: 7992062
    Abstract: A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: August 2, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Martin Saint-Laurent, Paul Bassett, Prayag Patel
  • Logic device and method supporting scan test
    Publication number: 20070300108
    Abstract: A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.
    Type: Application
    Filed: June 22, 2006
    Publication date: December 27, 2007
    Inventors: Martin Saint-Laurent, Paul Bassett, Prayag Patel