Patents by Inventor Precha Srisatuan

Precha Srisatuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Programmable logic device verification system and method
    Patent number: 6772381
    Abstract: A method and system for testing programmability of a programmable logic device (PLD) having a programmable AND array. The PLD is bulk programmed and verified. If the bulk programming fails, each row of cells of the AND array is programmed individually and the row-by-row programming of the PLD is verified.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: August 3, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Piyanuch Somchit, Precha Srisatuan, Lersak Nudach