Patents by Inventor Preecha JOYMAK

Preecha JOYMAK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11804416
    Abstract: A semiconductor device has a semiconductor die with a sensor and a cavity formed into a first surface of the semiconductor die to provide access to the sensor. A protective layer is formed on the first surface of the semiconductor die around the cavity. An encapsulant is deposited around the semiconductor die. The protective layer blocks the encapsulant from entering the cavity. With the cavity clear of encapsulant, liquid or gas has unobstructed entry into cavity during operation of the semiconductor die. The clear entry for the cavity provides reliable sensor detection and measurement. The semiconductor die is disposed over a leadframe. The semiconductor die has a sensor. The protective layer can be a film. The protective layer can have a beveled surface. A surface of the leadframe can be exposed from the encapsulant. A second surface of the semiconductor die can be exposed from the encapsulant.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: October 31, 2023
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Saravuth Sirinorakul, Preecha Joymak, Natawat Kasikornrungroj, Wasu Aingkaew, Kawin Saiubol, Thanawat Jaengkrajarng
  • Publication number: 20220077019
    Abstract: A semiconductor device has a semiconductor die with a sensor and a cavity formed into a first surface of the semiconductor die to provide access to the sensor. A protective layer is formed on the first surface of the semiconductor die around the cavity. An encapsulant is deposited around the semiconductor die. The protective layer blocks the encapsulant from entering the cavity. With the cavity clear of encapsulant, liquid or gas has unobstructed entry into cavity during operation of the semiconductor die. The clear entry for the cavity provides reliable sensor detection and measurement. The semiconductor die is disposed over a leadframe. The semiconductor die has a sensor. The protective layer can be a film. The protective layer can have a beveled surface. A surface of the leadframe can be exposed from the encapsulant. A second surface of the semiconductor die can be exposed from the encapsulant.
    Type: Application
    Filed: August 6, 2021
    Publication date: March 10, 2022
    Applicant: UTAC Headquarters Pte. Ltd.
    Inventors: Saravuth Sirinorakul, Preecha Joymak, Natawat Kasikornrungroj, Wasu Aingkaew, Kawin Saiubol, Thanawat Jaengkrajarng
  • Patent number: 10658277
    Abstract: Embodiments of the present invention are directed to a semiconductor package with improved thermal performance. The semiconductor package includes a package substrate comprising a top substrate surface and a bottom substrate surface. The package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface. A heat spreader is disposed on the top substrate surface. The heat spreader comprises a thickness extending from a top planar surface to a bottom planar surface of the heat spreader. The top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region. A semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region. The thickness of the heat spreader is greater relative to the thickness of the package substrate.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: May 19, 2020
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Antonio Bambalan Dimaano, Jr., Nataporn Charusabha, Saravuth Sirinorakul, Preecha Joymak, Roel Adeva Robles
  • Publication number: 20190051585
    Abstract: Embodiments of the present invention are directed to a semiconductor package with improved thermal performance. The semiconductor package includes a package substrate comprising a top substrate surface and a bottom substrate surface. The package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface. A heat spreader is disposed on the top substrate surface. The heat spreader comprises a thickness extending from a top planar surface to a bottom planar surface of the heat spreader. The top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region. A semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region. The thickness of the heat spreader is greater relative to the thickness of the package substrate.
    Type: Application
    Filed: August 7, 2018
    Publication date: February 14, 2019
    Inventors: Antonio Bambalan DIMAANO JR., Nataporn CHARUSABHA, Saravuth SIRINORAKUL, Preecha JOYMAK, Roel Adeva ROBLES