Abstract: The various functions that are desirable for interior test memory within a memory tester are implemented in Memory Sets each serving as the host for one or sometimes more of such functions. For certain classes of testing a portion of interior test memory can be used as a Stimulus Log RAM that operates as an ideal DUT to create the correct conditions that are to exist in an actual DUT after testing. The actual part can then be tested, while the expected receive vectors are taken from the Stimulus Log RAM, and the comparison results sent to an ECR, Tag RAM's, etc., as usual. In this way the test program does not have to create or contain within itself the particular receive vectors that are the expected response from the applied stimulus.

Abstract: DRAM speed of operation in an Error Catch RAM can be increased by a combination of interleaving signals for different Banks of memory in a Group thereof and multiplexing between those Groups of Banks. A three-way multiplexing between three Groups of four Banks each, combined with a flexible four-fold interleaving scheme for signals to a Group produces an increase in speed approaching a factor of twelve, while requiring only three memory busses. Each of the twelve Banks represents the entire available address space, and any individual write cycle might access any one of the twelve Banks. A utility mechanism composes results for all twelve Banks during a read cycle at an address into a unified result. There is a mechanism to track of the integrity of the composed results, as further write operations can produce the need for another composing step. There are four Memory Sets, two are “internal” SRAM's and two are “external” DRAM's.