Patents by Inventor Preetham Kumar

Preetham Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240380628
    Abstract: Systems and methods for facilitating a watch party are provided. In one example, a method includes: initiating a watch party session for a host user using, presenting content selected by the host user on a first user device during the watch party session, initiating a chat session concurrent with the watch party session, receiving a participation request by a guest user sent from a second user device for participating in the chat session; in response to the participation request, authenticating the guest user; presenting the content selected by the host user on the second user device; synchronizing the presentation of the content on the first user device with the presentation of the second user device; and facilitating communication between the host user and the guest user during the chat session.
    Type: Application
    Filed: May 23, 2024
    Publication date: November 14, 2024
    Inventors: Melvin P. Perinchery, Preetham Kumar
  • Patent number: 12034555
    Abstract: Systems and methods for facilitating a watch party are provided. In one example, a method includes: initiating a watch party session for a host user using, presenting content selected by the host user on a first user device during the watch party session, initiating a chat session concurrent with the watch party session, receiving a participation request by a guest user sent from a second user device for participating in the chat session; in response to the participation request, authenticating the guest user; presenting the content selected by the host user on the second user device; synchronizing the presentation of the content on the first user device with the presentation of the second user device; and facilitating communication between the host user and the guest user during the chat session.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: July 9, 2024
    Assignee: DISH Network Technologies India Private Limited
    Inventors: Melvin P. Perinchery, Preetham Kumar
  • Publication number: 20140068535
    Abstract: The present disclosure relates to methods and systems for designing and fabricating an integrated circuit. In particular, a method includes electronically searching a virtual layout of an integrated circuit to locate a dummy polysilicon structure positioned between adjacent terminals of first and second MOSFET devices that are connected to different nodes of the integrated circuit. The method includes changing a configuration of the dummy polysilicon structure of the virtual layout to extend an active silicon region adjacent to the dummy polysilicon structure and to form an electrical connection between the dummy polysilicon structure and one of a supply voltage node and a ground node of the integrated circuit.
    Type: Application
    Filed: September 19, 2012
    Publication date: March 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Ismayil Arafath Babu, Babruwahan Gade, Preetham Kumar
  • Patent number: 6998930
    Abstract: A miniaturized planar microstrip balun includes first and second microstrip coupling segments that are considerably shorter than a quarter of a guide wavelength (?g/4 ). In at least one embodiment, a microstrip balun is provided that does not require the use of lumped circuit elements or short circuit terminations.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: February 14, 2006
    Assignee: Intel Corporation
    Inventors: Justin Tabatchnick, Jeffrey Johnson, B Preetham Kumar, Gopal Thakkar
  • Patent number: 6591409
    Abstract: A method and system of measuring layout efficiency is disclosed wherein after the initial layout (A), and the layout is drawn (B) a layout verification step C includes identifying seed devices or layers and the devices or layers are grown according to design rules and process rules to determine the minimum area required for the design. The layout verification is performed for both device packing density and interconnect packing density and the efficiency is calculated based on the total available area and reported.(D).
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: July 8, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Ganesh Kamath, Preetham Kumar, Alec Morton
  • Publication number: 20020066064
    Abstract: A method and system of measuring layout efficiency is disclosed wherein after the initial layout (A), and the layout is drawn (B) a layout verification step C includes identifying seed devices or layers and the devices or layers are grown according to design rules and process rules to determine the minimum area required for the design. The layout verification is performed for both device packing density and interconnect packing density and the efficiency is calculated based on the total available area and reported.(D).
    Type: Application
    Filed: November 28, 2001
    Publication date: May 30, 2002
    Inventors: Ganesh Kamath, Preetham Kumar, Alec Morton