Patents by Inventor Preethi Sama

Preethi Sama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10656205
    Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: May 19, 2020
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Mark Semmelmeyer, Ali Vahidsafa, Sebastian Turullols, Scott Cooke, Senthilkumar Diraviam, Preethi Sama
  • Publication number: 20190235023
    Abstract: Embodiments include systems and methods for in-system, scan-based device testing using novel narrow-parallel (NarPar) implementations. Embodiments include a virtual automated test environment (VATE) system that can be disposed within the operating environment of an integrated circuit for which scan-based testing is desired (e.g., a chip under test, or CuT). For example, the VATE system is coupled with a service processor and with the CuT via a novel NarPar interface. A sequence controller can drive a narrow set of parallel scan pins on the CuT via the NarPar interface of the VATE system in accordance with an adapted test sequence having bit vector stimulants and expected responses. Responses of the CuT to the bit vector stimulants can be read out and compared to the expected results for scan-based testing of the chip.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 1, 2019
    Inventors: MARK SEMMELMEYER, ALI VAHIDSAFA, SEBASTIAN TURULLOLS, SCOTT COOKE, SENTHILKUMAR DIRAVIAM, PREETHI SAMA