Abstract: Synthesizing a schedule representation from a process model includes: defining a process model for a project plan by capturing model parameters and process flow; performing quantitative analysis on the process model, such as, for example, stochastic and queuing analysis; and synthesizing a schedule representation from the process model. In an exemplary embodiment, a discrete event simulation engine is used to synthesize a schedule representation from a process model. In an exemplary embodiment, the synthesized schedule is exported to a project viewer capable of interacting with one or more users. The system and method may include receiving one or more plan change and/or decision inputs, modifying the process model based on such inputs, performing quantitative analysis on the modified process model, and synchronizing the modified process model and the schedule representation.

Abstract: A computer-aided synthesis and verification tool is provided for modeling a digital device at a behavioral level and for synthesizing to a structural level utilizing user-defined attributes. The behavioral level is represented as a Data Dependency Graph (DDG) having a plurality of operations (shown as nodes) and operands (shown as arcs) which connect the nodes. Each operation or node is represented as a graphical icon, wherein the icon can have user-defined attributes associated with it. The attributes, nodes, and arcs are compiled and reduced to a Register Transfer Level (RTL) simulation model compatible with present VHDL and Verilog formats. Conversion from a behavioral model to an RTL model includes monitoring the internal states at rising clock edges and constructing states, events and event transistions (i.e., control path information) for each data value in the matrix of values within the data path.

Abstract: A custom simulation engine is provided which operates upon a set of statically scheduled events. The simulation engine is automatically created from a functional description of the integrated circuit design. Each element of each partition within the functional description is analyzed and events related to the element are scheduled. The statically scheduled events are used to produce scheduled source code, which is then compiled to produce the simulation engine. VHDL or Verilog descriptions are similarly automatically created from the functional description. Subsequently, the VHDL or Verilog descriptions are synthesized into a netlist describing a final design of an integrated circuit. The entire process is automatic, and so the simulation engine and the netlist are functionally equivalent by construction. No simulation of the VHDL or Verilog descriptions is required as the present simulation engine correctly represents the design. Manual development of a custom simulation engine is eliminated.