Patents by Inventor Prem Puri

Prem Puri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10602973
    Abstract: The present relates to a method, system and a device for non-invasive detection of urine flow from the bladder into the kidney(s). The method, system and device rely on measurements made at distinct time points and can be used to detect Vesicoureteral reflux. The method, system and device are designed to detect changes in urine volume in the ureter(s), bladder and/or kidney(s). The method and device measure conductivity changes by bioelectrical impedance or electrical impedance tomography technology.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: March 31, 2020
    Assignee: National University of Ireland, Galway
    Inventors: Sarah Loughney, Mark Bruzzi, Martin O'Halloran, Prem Puri, Ricardo Eleuterio
  • Publication number: 20180263546
    Abstract: The present relates to a method, system and a device for non-invasive detection of urine flow from the bladder into the kidney(s). The method, system and device rely on measurements made at distinct time points and can be used to detect Vesicoureteral reflux. The method, system and device are designed to detect changes in urine volume in the ureter(s), bladder and/or kidney(s). The method and device measure conductivity changes by bioelectrical impedance or electrical impedance tomography technology.
    Type: Application
    Filed: May 6, 2016
    Publication date: September 20, 2018
    Inventors: Sarah LOUGHNEY, Mark BRUZZI, Martin O'HALLORAN, Prem PURI, Ricardo ELEUTERIO
  • Patent number: 4477902
    Abstract: A testing technique is disclosed for assuring AC performance of high speed random logic, employing a low speed tester. AC testing on a low speed tester is split into multiple phases. During the first phase, a slack time delta is introduced, which is the time difference between the product cycle time required by the application and the tester cycle time used in the product test. The product is tested with this timing using conventionally generated test patterns. The effect of the slack is then resolved in the subsequent phases of the test. The product is tested again with the same type test patterns as in the first phase, but with redefined strobe times at the staging latches in the circuit. The slack delta is transferred to paths between the consecutive staging latches and the resultant signals arrive and get sampled by the low speed tester as if there were no slack.
    Type: Grant
    Filed: June 18, 1982
    Date of Patent: October 16, 1984
    Assignee: IBM Corporation
    Inventors: Prem Puri, Yogi K. Puri