Abstract: A machine-to-machine (M2M) partner automates all program parameter calculations through scripting or programming during an end-to-end encryption and decryption process. A platform dynamically scripts or programs the calculation of the encryption parameters and automatic response to alarms and alerts or to protect data transfers. The dynamic scripting effectively causes the same platform to be a different custom version for each value of parameters. Different custom versions of the platform encryption engines are not interoperable with each other or with a standard version. Variable and flexible multi-faceted unpredictable authentication methods authorize communication nodes. The platform performs multiple-stage checking of version, key, and password. The platform controller scrubs memory before exiting. A “Seed Packet” of data is used algorithmically to generate a sequence of random data to both generate and make use of an encryption key and password.

Abstract: A random data generator, a method, and a non-transitory machine-readable medium each operate a plurality of random number generators. Each random number generator is coupled to receive inputs comprising seed numbers, and generates an output stream of n-bit numbers. A bit-swap module receives each n-bit number and reorders the bits of the n-bit number to provide a reordered n-bit number. A byte select circuit selects a byte from the reordered n-bit number and provides a selected byte as an output to the random data stream.

Abstract: A random data generator, a method, and a non-transitory machine-readable medium each operate a plurality of random number generators. Each random number generator is coupled to receive inputs comprising seed numbers, and generates an output stream of n-bit numbers. A bit-swap module receives each n-bit number and reorders the bits of the n-bit number to provide a reordered n-bit number. A byte select circuit selects a byte from the reordered n-bit number and provides a selected byte as an output to the random data stream.

Abstract: A processor for collecting boolean conditions of multiple operations includes a condition collection register which may be written and read in parallel or written serially and into which a single bit is shifted from either the left or the right, and a processor instruction decoder that decodes one operand register addresses as a read address for the condition collection register, and three operand register addresses as a write address for said condition collection register.

Abstract: An arithmetic logic unit includes structure for calculating in at least two stages, this structure including substructure for calculating in each of the at least two stages at least partially at the same time and substructure for ensuring the substructure for calculating in each of the at least two stages performs only one calculation at a time. Accumulators that work with pipe stages of a floating point unit may form all of part of the calculating structure. A method of performing calculations includes the steps of separating the calculations into at least two stages and separately accumulating the results of the stages using at least two accumulators, one each accumulator for each calculation at each of the at least two stages.

Abstract: A floating point processor for pipelining a series of calculations of simple and compound arithmetic operations includes at least one arithmetic operation unit for performing arithmetic operations on input operands provided to the arithmetic operation units and at least one accumulator for storing the results of the arithmetic operations performed by the arithmetic operation unit. The results stored in the accumulators are then provided to the arithmetic operation units. Arithmetic operations are pipelined through the floating point processor by a series of latches which sequence the input operands, results produced by the arithmetic operation units using the input operands, and results produced by the arithmetic operation units using the input operands and the accumulated operands.