Patents by Inventor Preston Allen Thomson
Preston Allen Thomson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11735269Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.Type: GrantFiled: January 31, 2022Date of Patent: August 22, 2023Assignee: Micron Technology, Inc.Inventors: Ting Luo, Kulachet Tanpairoj, Harish Reddy Singidi, Jianmin Huang, Preston Allen Thomson, Sebastien Andre Jean
-
Patent number: 11610632Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.Type: GrantFiled: May 26, 2021Date of Patent: March 21, 2023Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Allen Thomson, Harish Reddy Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
-
Patent number: 11513889Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: August 26, 2021Date of Patent: November 29, 2022Assignee: Micron Technology, Inc.Inventors: Chun Sum Yeung, Falgun G. Trivedi, Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Ting Luo, Jianmin Huang
-
Patent number: 11487612Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: September 10, 2020Date of Patent: November 1, 2022Assignee: Micron Technology, Inc.Inventors: Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Michael G. McNeeley
-
Patent number: 11482298Abstract: A method of operating a memory device comprises generating a target voltage using a pump circuit of the memory device, the target voltage to be applied to a word line or pillar of a memory cell of the memory device; providing an indication of current generated by the pump circuit after the pump circuit output reaches the target voltage; and determining when the current generated by the pump circuit is greater than a specified threshold current and generating a fault indication according to the determination.Type: GrantFiled: May 29, 2020Date of Patent: October 25, 2022Assignee: Micron Technology, Inc.Inventors: Jason Lee Nevill, Preston Allen Thomson, Chi Ming Chu, Sheng-Huang Lee
-
Publication number: 20220157386Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Ting Luo, Kulachet Tanpairoj, Harish Reddy Singidi, Jianmin Huang, Preston Allen Thomson, Sebastien Andre Jean
-
Patent number: 11288149Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is provisionally removed from service in response to encountering read errors in the first memory block. Memory pages of the first memory block are tested in a second mode comprising reading memory pages at different read voltages. A raw bit error rate (RBER) or a read window budget (RWB) is determined for memory pages at the different read voltages and the provisionally removed first memory block is returned to service or retired based on the determined RBER or the RWB.Type: GrantFiled: October 7, 2020Date of Patent: March 29, 2022Assignee: Micron Technology, Inc.Inventors: Harish Reddy Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Allen Thomson
-
Patent number: 11238939Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.Type: GrantFiled: January 26, 2021Date of Patent: February 1, 2022Assignee: Micron Technology, Inc.Inventors: Ting Luo, Kulachet Tanpairoj, Harish Reddy Singidi, Jianmin Huang, Preston Allen Thomson, Sebastien Andre Jean
-
Publication number: 20210390014Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: August 26, 2021Publication date: December 16, 2021Inventors: Chun Sum Yeung, Falgun G. Trivedi, Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Ting Luo, Jianmin Huang
-
Publication number: 20210375387Abstract: A method of operating a memory device comprises generating a target voltage using a pump circuit of the memory device, the target voltage to be applied to a word line or pillar of a memory cell of the memory device; providing an indication of current generated by the pump circuit after the pump circuit output reaches the target voltage; and determining when the current generated by the pump circuit is greater than a specified threshold current and generating a fault indication according to the determination.Type: ApplicationFiled: May 29, 2020Publication date: December 2, 2021Inventors: Jason Lee Nevill, Preston Allen Thomson, Chi Ming Chu, Sheng-Huang Lee
-
Publication number: 20210287748Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.Type: ApplicationFiled: May 26, 2021Publication date: September 16, 2021Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Allen Thomson, Harish Reddy Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
-
Patent number: 11106530Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: December 20, 2019Date of Patent: August 31, 2021Assignee: Micron Technology, Inc.Inventors: Chun Sum Yeung, Falgun G. Trivedi, Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Ting Luo, Jianmin Huang
-
Publication number: 20210191807Abstract: A variety of applications can include apparatus and/or methods that provide parity data protection to data in a memory system for a limited period of time and not stored as permanent parity data in a non-volatile memory. Parity data can be accumulated in a volatile memory for data programmed via a group of access lies having a specified number of access lines in the group. A read verify can be issued to selected pages after programming finishes at the end of programming via the access lines of the group. With the programming of the data determined to be acceptable at the end of programming via the last of the access lines of the group, the parity data in the volatile memory can be discarded and accumulation can begin for a next group having a specified number of access lines. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Inventors: Chun Sum Yeung, Falgun G. Trivedi, Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Ting Luo, Jianmin Huang
-
Patent number: 11037630Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.Type: GrantFiled: April 23, 2020Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Allen Thomson, Harish Reddy Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
-
Publication number: 20210151111Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.Type: ApplicationFiled: January 26, 2021Publication date: May 20, 2021Inventors: Ting Luo, Kulachet Tanpairoj, Harish Reddy Singidi, Jianmin Huang, Preston Allen Thomson, Sebastien Andre Jean
-
Patent number: 10950310Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.Type: GrantFiled: December 26, 2019Date of Patent: March 16, 2021Assignee: Micron Technology, Inc.Inventors: Ting Luo, Kulachet Tanpairoj, Harish Reddy Singidi, Jianmin Huang, Preston Allen Thomson, Sebastien Andre Jean
-
Publication number: 20210019241Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is provisionally removed from service in response to encountering read errors in the first memory block. Memory pages of the first memory block are tested in a second mode comprising reading memory pages at different read voltages. A raw bit error rate (RBER) or a read window budget (RWB) is determined for memory pages at the different read voltages and the provisionally removed first memory block is returned to service or retired based on the determined RBER or the RWB.Type: ApplicationFiled: October 7, 2020Publication date: January 21, 2021Inventors: Harish Reddy Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Allen Thomson
-
Publication number: 20200409789Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: September 10, 2020Publication date: December 31, 2020Inventors: Harish Reddy Singidi, Xiangang Luo, Preston Allen Thomson, Michael G. McNeeley
-
Patent number: 10824527Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.Type: GrantFiled: July 5, 2019Date of Patent: November 3, 2020Assignee: Micron Technology, Inc.Inventors: Harish Reddy Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Allen Thomson
-
Publication number: 20200258578Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.Type: ApplicationFiled: April 23, 2020Publication date: August 13, 2020Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Allen Thomson, Harish Reddy Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang