Abstract: The present invention provides a method and apparatus for performing floating-point operations. The apparatus of the present invention comprises a floating point unit which comprises standard multiply accumulate units (MACs) which are capable of performing multiply accumulate operations on a plurality of data type formats. The standard MACs are configured to operate on traditional data type formats and on single instruction multiple data (SIMD) type formats. Therefore, dedicated SIMD MAC units are not needed, thus allowing a significant savings in die area to be realized. When a SIMD instruction is to be operated on by one of the MAC units, the data is presented to the upper and lower MAC units as 64-bit words. Each MAC unit also receives one or more bits which cause the MAC units to each select either the upper or lower halves of the 64-bit words. Each MAC unit then operates on its respective 32-bit words.

Abstract: The present invention provides a method and apparatus for performing load bypasses with data conversion in a floating-point unit. This process of reading instructions and data out of a cache memory component, of decoding the instructions, of performing the a memory-format-to-register format conversion and of writing the converted data to the register file block of a floating-point unit is known as a load operation. A load operation occurs over many cycles. In accordance with the present invention, the number of cycles required to perform a load operation has been shortened, thereby dramatically increasing the overall throughput of the floating-point unit. In accordance with the present invention, the floating-point unit performs a load bypass with conversion, which significantly shortens the load operation. Data received by the floating-point unit must be converted from a memory format into a register format.

Abstract: An integrated circuit chip responds to clock waves having differing frequencies at different times. The chip includes a semiconductor memory cell having a write enable input terminal responsive to a write enable signal having first and second levels. The cell has a tendency to operate improperly in response to the first level of the write enable signal having an excessively long predetermined duration. A write enable signal source responds to the clock waves so that for clock waves having half cycles of duration less than the predetermined duration the first level of the write enable signal has durations approximately equal to the durations of the half cycles of these clock waves. For clock waves having half cycles of duration greater than the predetermined duration, the first level of the write enable signal has a duration substantially equal to the predetermined duration.