Patents by Inventor Preston P. Briggs, III

Preston P. Briggs, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Resiliency to memory failures in computer systems
    Patent number: 9535804
    Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: January 3, 2017
    Assignee: Cray Inc.
    Inventors: Laurence S. Kaplan, Preston P. Briggs, III, Miles A. Ohlrich, Willard H. Leslie
  • RESILIENCY TO MEMORY FAILURES IN COMPUTER SYSTEMS
    Publication number: 20130311823
    Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.
    Type: Application
    Filed: May 21, 2012
    Publication date: November 21, 2013
    Inventors: Laurence S. Kaplan, Preston P. Briggs, III, Miles A. Ohlrich, Willard H. Leslie