Patents by Inventor Preston Pengra Briggs
Preston Pengra Briggs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934876Abstract: A compiler-implemented technique for performing a storage allocation is described. Computer code to be converted into machine instructions for execution on an integrated circuit device is received. Based on the computer code, a set of values that are to be stored on the integrated circuit device are determined. An interference graph that includes the set of values and a set of interferences is constructed. A number of possible placements and a number of blocked placements in a memory of the integrated circuit device are computed for each of the set of values. At least a portion of the set of values are assigned to a set of memory locations in the memory based on the numbers of possible placements and blocked placements, resulting in a set of memory location assignments.Type: GrantFiled: June 9, 2021Date of Patent: March 19, 2024Assignee: Amazon Technologies, Inc.Inventor: Preston Pengra Briggs
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Patent number: 11797280Abstract: Techniques to partition a neural network model for serial execution on multiple processing integrated circuit devices are described. An initial partitioning of the model into multiple partitions each corresponding to a processing integrated circuit device is performed. For each partition, an execution latency is calculated by aggregating compute clock cycles to perform computations in the partition, and weight loading clock cycles determined based on a number of weights used in the partition. The amount of data being outputted from the partition is also determined. The partitions can be adjusted by moving computations from a source partition to a target partition to change execution latencies of the partitions and the amount of data being transferred between partitions.Type: GrantFiled: June 30, 2021Date of Patent: October 24, 2023Assignee: Amazon Technologies, Inc.Inventors: Parivallal Kannan, Fabio Nonato de Paula, Preston Pengra Briggs
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Patent number: 11775268Abstract: A compiler-implemented technique for performing a storage allocation is described. Computer code to be converted into machine instructions for execution on an integrated circuit device is received. The integrated circuit device includes a memory having a set of memory locations. Based on the computer code, a set of values that are to be stored on the integrated circuit device are determined. An interference graph that includes the set of values and a set of interferences is constructed. While traversing the interference graph, a set of memory location assignments are generated by assigning the set of values to the set of memory locations in accordance with one or more color selection schemes.Type: GrantFiled: June 8, 2021Date of Patent: October 3, 2023Assignee: Amazon Technologies, Inc.Inventors: Preston Pengra Briggs, Ron Diamant, Robert Geva
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Patent number: 11625269Abstract: A technique for scheduling instructions includes obtaining a set of instructions that operate on memory objects, and determining the dependencies of the memory objects. The memory objects are then sorted into a sequence of memory objects based on the dependencies of the memory objects, and the set of instructions are scheduled into a sequence of instructions according to the sequence of memory objects. Sorting memory objects allows instructions that operate on the same memory object to be kept together. This helps minimize spilling conditions because intervening instructions that do not operate on the same memory object can be avoided.Type: GrantFiled: March 31, 2021Date of Patent: April 11, 2023Assignee: Amazon Technologies, Inc.Inventors: Robert Geva, Taylor Goodhart, Ron Diamant, Preston Pengra Briggs
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Patent number: 11144291Abstract: Methods of accelerating the execution of neural networks are disclosed. A description of a neural network may be received. A plurality of operators may be identified based on the description of the neural network. A plurality of symbolic models associated with the plurality of operators may be generated. For each symbolic model, a nested loop associated with an operator may be identified, a loop order may be defined, and a set of data dependencies may be defined. A set of inter-operator dependencies may be extracted based on the description of the neural network. The plurality of symbolic models and the set of inter-operator dependencies may be analyzed to identify a combinable pair of nested loops. The combinable pair of nested loops may be combined to form a combined nested loop.Type: GrantFiled: November 27, 2019Date of Patent: October 12, 2021Assignee: Amazon Technologies, Inc.Inventors: Hongbin Zheng, Preston Pengra Briggs, Tobias Joseph Kastulus Edler von Koch, Taemin Kim, Randy Renfu Huang
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Patent number: 10884859Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.Type: GrantFiled: April 16, 2019Date of Patent: January 5, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
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Publication number: 20190243710Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.Type: ApplicationFiled: April 16, 2019Publication date: August 8, 2019Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
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Patent number: 10324792Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.Type: GrantFiled: June 16, 2017Date of Patent: June 18, 2019Assignee: Cray Inc.Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
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Patent number: 10127109Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.Type: GrantFiled: June 16, 2017Date of Patent: November 13, 2018Assignee: Cray, Inc.Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
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Patent number: 9910731Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.Type: GrantFiled: November 21, 2016Date of Patent: March 6, 2018Assignee: Cray Inc.Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
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Publication number: 20170308430Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.Type: ApplicationFiled: June 16, 2017Publication date: October 26, 2017Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
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Publication number: 20170286240Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.Type: ApplicationFiled: June 16, 2017Publication date: October 5, 2017Inventors: Laurence S. Kaplan, Preston Pengra Briggs Ill, Miles Arthur Ohlrich, Willard Huston Leslie
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Publication number: 20170068596Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.Type: ApplicationFiled: November 21, 2016Publication date: March 9, 2017Inventors: Laurence S. Kaplan, Preston Pengra Briggs, III, Miles Arthur Ohlrich, Willard Huston Leslie
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Patent number: 7739667Abstract: A system for conducting performance analysis for executing tasks. The analysis involves generating a variety of trace information related to performance measures, including parallelism-related information, during execution of the task. In order to generate the trace information, target source code of interest is compiled in such a manner that executing the resulting executable code will generate execution trace information composed of a series of events. Each event stores trace information related to a variety of performance measures for the one or more processors and protection domains used. After the execution trace information has been generated, the system can use that trace information and a trace information description file to produce useful performance measure information. The trace information description file contains information that describes the types of execution events as well as the structure of the stored information.Type: GrantFiled: October 19, 2005Date of Patent: June 15, 2010Assignee: Cray Inc.Inventors: Charles David Callahan, II, Keith Arnett Shields, Preston Pengra Briggs, III
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Patent number: 6961925Abstract: A system for conducting performance analysis for executing tasks. The analysis involves generating a variety of trace information related to performance measures, including parallelism-related information, during execution of the task. In order to generate the trace information, target source code of interest is compiled in such a manner that executing the resulting executable code will generate execution trace information composed of a series of events. Each event stores trace information related to a variety of performance measures for the one or more processors and protection domains used. After the execution trace information has been generated, the system can use that trace information and a trace information description file to produce useful performance measure information. The trace information description file contains information that describes the types of execution events as well as the structure of the stored information.Type: GrantFiled: April 3, 2001Date of Patent: November 1, 2005Assignee: Cray Inc.Inventors: Charles David Callahan, II, Keith Arnett Shields, Preston Pengra Briggs, III
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Publication number: 20020129339Abstract: A system for conducting performance analysis for executing tasks. The analysis involves generating a variety of trace information related to performance measures, including parallelism-related information, during execution of the task. In order to generate the trace information, target source code of interest is compiled in such a manner that executing the resulting executable code will generate execution trace information composed of a series of events. Each event stores trace information related to a variety of performance measures for the one or more processors and protection domains used. After the execution trace information has been generated, the system can use that trace information and a trace information description file to produce useful performance measure information. The trace information description file contains information that describes the types of execution events as well as the structure of the stored information.Type: ApplicationFiled: April 3, 2001Publication date: September 12, 2002Inventors: Charles David Callahan, Keith Arnett Shields, Preston Pengra Briggs
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Patent number: 6230313Abstract: A system for conducting performance analysis for executing tasks. The analysis involves generating a variety of trace information related to performance measures, including parallelism-related information, during execution of the task. In order to generate the trace information, target source code of interest is compiled in such a manner that executing the resulting executable code will generate execution trace information composed of a series of events. Each event stores trace information related to a variety of performance measures for the one or more processors and protection domains used. After the execution trace information has been generated, the system can use that trace information and a trace information description file to produce useful performance measure information. The trace information description file contains information that describes the types of execution events as well as the structure of the stored information.Type: GrantFiled: December 23, 1998Date of Patent: May 8, 2001Assignee: Cray Inc.Inventors: Charles David Callahan, II, Keith Arnett Shields, Preston Pengra Briggs, III