Patents by Inventor Preston Thomson
Preston Thomson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10789126Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: October 9, 2018Date of Patent: September 29, 2020Assignee: Micron Technology, Inc.Inventors: Harish Reddy Singidi, Xiangang Luo, Preston Thomson, Michael G. McNeeley
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Publication number: 20200194092Abstract: A target vector representing a usage parameter corresponding to a test of a memory component is generated. A test sample is assigned to the target vector and a set of path variables are generated for the test sample. A test process of the test is executed using the test sample in accordance with the set of path variables to generate a test result. A failure associated with the test result is identified.Type: ApplicationFiled: December 17, 2018Publication date: June 18, 2020Inventors: Aswin Thiruvengadam, Sivagnanam Parthasarathy, Preston Thomson
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Patent number: 10636482Abstract: Methods of operating a memory include receiving a plurality of digits of data for programming to a plurality of memory cells of the memory, redistributing the received plurality of digits of data in a reversible manner to generate a plurality of digits of redistributed data each corresponding to a respective memory cell of the plurality of memory cells, and for each memory cell of the plurality of memory cells, programming the corresponding digit of redistributed data for that memory cell to a first digit position of a respective data state of that memory cell, programming a second digit of data having a first data value to a second digit position of the respective data state of that memory cell, and programming a third digit of data having a second data value to a third digit position of the respective data state of that memory cell.Type: GrantFiled: March 22, 2019Date of Patent: April 28, 2020Assignee: Micron Technology, Inc.Inventors: Preston A. Thomson, Peiling Zhang, Junchao Chen
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Publication number: 20200110661Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: October 9, 2018Publication date: April 9, 2020Inventors: Harish Reddy Singidi, Xiangang Luo, Preston Thomson, Michael G. McNeeley
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Patent number: 10529434Abstract: Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first physical page of a number of physical pages from an initial first read level position to a calibrated first read level position. The first read level may be between a first threshold voltage distribution corresponding to a first logical state of the at least four logical states and a second threshold voltage distribution corresponding to a second logical state of the at least four logical states. Also, the first threshold voltage distribution may be a highest threshold voltage distribution for the first physical page. The memory controller may calibrate a second read level for the first physical page that is lower than the first read level from an initial second read level position to a calibrated first read level position.Type: GrantFiled: September 12, 2018Date of Patent: January 7, 2020Assignee: Micron Technology, Inc.Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish Reddy Singidi, Ting Luo, Ashutosh Malshe, Preston Thomson, Jianmin Huang
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Patent number: 10522229Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.Type: GrantFiled: August 30, 2017Date of Patent: December 31, 2019Assignee: Micron Technology, Inc.Inventors: Ting Luo, Kulachet Tanpairoj, Harish Singidi, Jianmin Huang, Preston Thomson, Sebastien Andre Jean
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Publication number: 20190371409Abstract: A data erase operation is performed on the memory system. The directed data erase operation performed on the memory system erases blocks of the memory device including blocks that are indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as not including user data. In some embodiments, a data erase operation may be performed on a memory system to erase those groups of memory cells (e.g., blocks) indicated as valid without erasing those groups of memory cells (e.g., blocks) indicated as invalid. In some embodiments, a data erase operation that can be performed on a memory system may obtain information associated with failing scenes of groups of memory cells (e.g., blocks) prior to obtaining the information, and erase the blocks (e.g., invalid blocks) subsequently.Type: ApplicationFiled: May 31, 2018Publication date: December 5, 2019Inventors: Kevin R. Brandt, Adam J. Hieb, Jonathan Tanguy, Preston A. Thomson
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Patent number: 10452282Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.Type: GrantFiled: April 7, 2017Date of Patent: October 22, 2019Assignee: Micron Technology, Inc.Inventors: Kishore K. Muchherla, Sampath K. Ratnam, Peter Feeley, Michael G. Miller, Preston A. Thomson, Renato C. Padilla, Ashutosh Malshe
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Publication number: 20190278490Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.Type: ApplicationFiled: May 23, 2019Publication date: September 12, 2019Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
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Publication number: 20190267105Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.Type: ApplicationFiled: May 15, 2019Publication date: August 29, 2019Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
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Patent number: 10387281Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.Type: GrantFiled: August 30, 2017Date of Patent: August 20, 2019Assignee: Micron Technology, Inc.Inventors: Harish Reddy Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Thomson
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Patent number: 10360947Abstract: Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.Type: GrantFiled: August 31, 2017Date of Patent: July 23, 2019Assignee: Micron Technology, Inc.Inventors: Tyson M. Stichka, Preston Thomson, Scott Anthony Stoller, Christopher Bueb, Jianmin Huang, Kulachet Tanpairoj, Harish Singidi
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Publication number: 20190221258Abstract: Methods of operating a memory include receiving a plurality of digits of data for programming to a plurality of memory cells of the memory, redistributing the received plurality of digits of data in a reversible manner to generate a plurality of digits of redistributed data each corresponding to a respective memory cell of the plurality of memory cells, and for each memory cell of the plurality of memory cells, programming the corresponding digit of redistributed data for that memory cell to a first digit position of a respective data state of that memory cell, programming a second digit of data having a first data value to a second digit position of the respective data state of that memory cell, and programming a third digit of data having a second data value to a third digit position of the respective data state of that memory cell.Type: ApplicationFiled: March 22, 2019Publication date: July 18, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Preston A. Thomson, Peiling Zhang, Junchao Chen
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Patent number: 10354732Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.Type: GrantFiled: August 30, 2017Date of Patent: July 16, 2019Assignee: Micron Technology, Inc.Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Thomson, Harish Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
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Patent number: 10325670Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.Type: GrantFiled: September 12, 2018Date of Patent: June 18, 2019Assignee: Micron Technology, Inc.Inventors: Ting Luo, Scott Anthony Stoller, Preston Thomson, Devin Batutis, Harish Reddy Singidi, Kulachet Tanpairoj
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Patent number: 10325668Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.Type: GrantFiled: April 5, 2017Date of Patent: June 18, 2019Assignee: Micron Technology, Inc.Inventors: Kishore K. Muchherla, Ashutosh Malshe, Preston A. Thomson, Michael G. Miller, Gary F. Besinga, Scott A. Stoller, Sampath K. Ratnam, Renato C. Padilla, Peter Feeley
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Patent number: 10283195Abstract: Methods of operating a memory include receiving data for programming to a plurality of memory cells of the memory, redistributing the received data in a reversible manner, programming the redistributed data to the plurality of memory cells, and programming respective second data to each memory cell of the plurality of memory cells containing the redistributed data, wherein the respective second data for any memory cell of the plurality of memory cells has a same data value as the respective second data for each remaining memory cell of the plurality of memory cells.Type: GrantFiled: May 31, 2018Date of Patent: May 7, 2019Assignee: Micron Technology, Inc.Inventors: Preston A. Thomson, Peiling Zhang, Junchao Chen
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Publication number: 20190130981Abstract: Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first physical page of a number of physical pages from an initial first read level position to a calibrated first read level position. The first read level may be between a first threshold voltage distribution corresponding to a first logical state of the at least four logical states and a second threshold voltage distribution corresponding to a second logical state of the at least four logical states. Also, the first threshold voltage distribution may be a highest threshold voltage distribution for the first physical page. The memory controller may calibrate a second read level for the first physical page that is lower than the first read level from an initial second read level position to a calibrated first read level position.Type: ApplicationFiled: September 12, 2018Publication date: May 2, 2019Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish Reddy Singidi, Ting Luo, Ashutosh Malshe, Preston Thomson, Jianmin Huang
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Patent number: 10248594Abstract: The present disclosure is related to programming interruption management. An apparatus can be configured to detect an interruption during a programming operation and modify the programming operation to program a portion of the memory array to an uncorrectable state in response to detecting the interruption.Type: GrantFiled: August 3, 2018Date of Patent: April 2, 2019Assignee: Micron Technology, Inc.Inventors: Preston A. Thomson, Kishore K. Muchherla, Sampath K. Ratnam
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Publication number: 20190065331Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.Type: ApplicationFiled: August 30, 2017Publication date: February 28, 2019Inventors: Harish Singidi, Giuseppe Cariello, Deping He, Scott Anthony Stoller, Devin Batutis, Preston Thomson