Abstract: A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit.

Abstract: A field-effect transistor (FET) includes, a first drain, a second drain, a body and a gate region. The gate region has a length, and is configured and arranged to create, in response to a gate voltage, a channel that is in the body, between the first and second drains, and along the length of the gate region. A plurality of body dropdowns are located in the gate region and are spaced along a width of the gate region. Each of the body dropdowns are configured and arranged to provide an electrical contact to the body for biasing purposes.

Abstract: A semiconductor die is disclosed comprising a lateral semiconductor device on an upper major surface of a substrate, the integrated circuit comprising a silicon layer over the substrate, a recess in the silicon layer, a layer of LOCOS silicon oxide within the recess and having a grown upper surface which is coplanar with the surface of an un-recessed portion of the silicon layer, wherein the silicon layer beneath the recess has a non-uniform lateral doping profile, and is comprised in a drift region of the lateral semiconductor device. A method of making such a die is also disclosed, as is an integrated circuit and a driver circuit.

Abstract: There is disclosed a semiconductor device. The device comprises: a silicon layer; a tapered insulating layer formed on the silicon layer; and a plurality of Bipolar CMOS DMOS device layers formed above the tapered insulating layer. The taper of the tapered insulating layer is in the lower surface of the tapered insulating layer. The tapered insulating layer has a substantially planar upper surface and is at least partially recessed in the silicon layer.