Abstract: A system includes a plurality of inputs each configured to receive a filtered version of a source signal. The system extracts the energy information from each input signal and compares the energy information of a plurality of input signals. Alternatively, the system extracts energy information from a signal that is the difference of two input signals. Based on the energy information, the system determines at least one parameter that may be changed in at least one circuit in a plurality of circuits to minimize the differences in energy of the input signals or to minimize the energy of the difference signal. Parameters may include for example amplification, delay, and corner frequency values. The set of circuits may include microphone interface circuits. Merely by way of example, a system with microphone interface circuits may be included in a hearing enhancement device or in a hands-free earpiece.

Abstract: A system includes a plurality of inputs each configured to receive a filtered version of a source signal. The system extracts the energy information from each input signal and compares the energy information of a plurality of input signals. Alternatively, the system extracts energy information from a signal that is the difference of two input signals. Based on the energy information, the system determines at least one parameter that may be changed in at least one circuit in a plurality of circuits to minimize the differences in energy of the input signals or to minimize the energy of the difference signal. Parameters may include for example amplification, delay, and corner frequency values. The set of circuits may include microphone interface circuits. Merely by way of example, a system with microphone interface circuits may be included in a hearing enhancement device or in a hands-free earpiece.

Abstract: An integrated circuit (200) includes a translator circuit (210) for translating from a lower logic-level voltage range signal (101(a), 101(b)) to a higher logic-level voltage range signal (141(a), 141(b)). The translator (210) includes a differential input stage (110) including a first (Q39) and a second input transistor (Q38) coupled to receive at least a first input signal (101(a), 101(b)) that defines the lower voltage range signal. A voltage follower 120 includes first and second follower transistors (Q41, Q40). An output of the first and second input transistors (Q39, Q38) is coupled to inputs of the first and second follower transistors (Q41, Q40). A dynamic gain boosting switching circuit (130) is coupled to receive outputs from the first and second follower transistors (Q41, Q40) and includes a first and a second control node (131, 132).

Abstract: An integrated circuit (100) includes a current mode write driver (105). The write driver (105) includes a switching control circuit (110) including (i) a DC current control circuit (111) operable to directly convert a received ECL differential signal into first, second, third and fourth DC output currents (a, b, c, and d) and (ii) a boost current control circuit (112) operable to directly convert a received level shifted version of the ECL differential voltage signal and a delayed version of the ECL differential voltage signal into first, second, third and fourth boost output currents (a1, b1, c1, and d1). An H-bridge circuit (120) includes an output stage (125) including first and second current sourcing control nodes (126, 127) and first and second current sinking control nodes (128, 129). A first output node (131) is between the first sourcing and first sinking nodes (126, 128) and second output node between the second sourcing and the second sinking nodes (127, 129).

Abstract: An integrated circuit (200) includes a translator circuit (210) for translating from a lower logic-level voltage range signal (101(a), 101(b)) to a higher logic-level voltage range signal (141(a), 141(b)). The translator (210) includes a differential input stage (110) including a first (Q39) and a second input transistor (Q38) coupled to receive at least a first input signal (101(a), 101(b)) that defines the lower voltage range signal. A voltage follower 120 includes first and second follower transistors (Q41, Q40). An output of the first and second input transistors (Q39, Q38) is coupled to inputs of the first and second follower transistors (Q41, Q40). A dynamic gain boosting switching circuit (130) is coupled to receive outputs from the first and second follower transistors (Q41, Q40) and includes a first and a second control node (131, 132).