Patents by Inventor Pritesh Mahadev Pawaskar

Pritesh Mahadev Pawaskar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10691190
    Abstract: The disclosed technology provides methods for performing a power delivery network analysis of the memory unit I/O power domain. The methods include performing a signal and power integrity analysis for a memory unit I/O power domain to extract characteristics of a current waveform, determining characteristics of an expected waveform based on a current response for the memory unit I/O power domain, and determining whether the characteristics of the current waveform and the characteristics of the expected waveform are within a tolerance limit. The method also includes various remedial operations and CPM regeneration which may iteratively occur until the waveform matches and final CPM is generated which is use for PDN analysis.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 23, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Nitin Kumar Chhabra, Pritesh Mahadev Pawaskar
  • Publication number: 20190108301
    Abstract: A method of generating a chip power model (CPM) for a chip by determining a current profile measurement on a validation board for the chip, and stressing the chip using a plurality of stress factors. A stressed measured waveform is captured and stored. A CPM is generated with the measured waveform captured using the plurality of stress factors. A simulation waveform is captured and stored from the CPM. The measured and simulation waveforms are compared, and when the measured and simulation waveforms do not match, at least one parameter of the CPM is modified iteratively until the measured and simulation waveforms match.
    Type: Application
    Filed: October 5, 2017
    Publication date: April 11, 2019
    Inventors: Nitin Kumar Chhabra, Pritesh Mahadev Pawaskar, William Harrison Hempy, II, Gaurav Mathur
  • Publication number: 20180373302
    Abstract: The disclosed technology provides methods for performing a power delivery network analysis of the memory unit I/O power domain. The methods include performing a signal and power integrity analysis for a memory unit I/O power domain to extract characteristics of a current waveform, determining characteristics of an expected waveform based on a current response for the memory unit I/O power domain, and determining whether the characteristics of the current waveform and the characteristics of the expected waveform are within a tolerance limit. The method also includes various remedial operations and CPM regeneration which may iteratively occur until the waveform matches and final CPM is generated which is use for PDN analysis.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Nitin Kumar Chhabra, Pritesh Mahadev Pawaskar