Patents by Inventor Prithviraj Banerjee
Prithviraj Banerjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11941629Abstract: This disclosure describes techniques for providing instructions when receiving biometric data associated with a user. For instance, a device may detect a portion of a user, such as a hand. The device may then display a first graphical element indicating a target location for placing the portion of the user above the user-recognition device. Additionally, the device may determine locations of the portion of the user above the device. The device may then display a second graphical element indicating the locations, such as when the locations are not proximate to the target location. Additionally, the device may display instructions for moving the portion of the user to the target location. Based on detecting that the location of the portion of the user is proximate to the target location, the device may send data representing the portion of the user to a remote system.Type: GrantFiled: September 27, 2019Date of Patent: March 26, 2024Assignee: Amazon Technologies, Inc.Inventors: Nichole Stockman, Korwin Jon Smith, Douglas Andrew Hungarter, Joshua Adam Cowan, Jared Corso, Rajeev Ranjan, Prithviraj Banerjee, Matthew Christopher Smith
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Patent number: 11868443Abstract: A neural network is trained to process input data and generate a classification value that characterizes the input with respect to an ordered continuum of classes. For example, the input data may comprise an image and the classification value may be indicative of a quality of the image. The ordered continuum of classes may represent classes of quality of the image ranging from “worst”, “bad”, “normal”, “good”, to “best”. During training, loss values are determined using an ordered classification loss function. The ordered classification loss function maintains monotonicity in the loss values that corresponds to placement in the continuum. For example, the classification value for a “bad” image will be less than the classification value indicative of a “best” image. The classification value may be used for subsequent processing. For example, biometric input data may be required to have a minimum classification value for further processing.Type: GrantFiled: May 12, 2021Date of Patent: January 9, 2024Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Rajeev Ranjan, Prithviraj Banerjee, Manoj Aggarwal, Gerard Guy Medioni, Dilip Kumar
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Patent number: 11861927Abstract: Actors may be detected and tracked within a scene using multiple imaging devices provided in a network that are aligned with fields of view that overlap at least in part. Processors operating on the imaging devices may evaluate the images using one or more classifiers to recognize body parts within the images, and to associate the body parts with a common actor within the scene. Each of the imaging devices may generate records of the positions of the body parts and provide such records to a central server, that may correlate body parts appearing within images captured by two or more of the imaging devices and generate a three-dimensional model of an actor based on positions of the body parts. Motion of the body parts may be tracked in subsequent images, and the model of the actor may be updated based on the motion.Type: GrantFiled: January 24, 2022Date of Patent: January 2, 2024Assignee: Amazon Technologies, Inc.Inventors: Prithviraj Banerjee, Leonid Pishchulin, Jean Laurent Guigues, Gerard Guy Medioni
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Patent number: 11816932Abstract: This disclosure describes techniques for identifying users that are enrolled for use of a user-recognition system and updating identification data of these users over time. To enroll in the user-recognition system, the user may initially scan his or her palm. The resulting image data may later be used when the user requests to be identified by the system by again scanning his or her palm. However, because the characteristics of user palms may change over the time, the user-recognition system may periodically perform processes for updating the identification data stored in association with the user in order to maintain or increase an accuracy of the user-recognition system.Type: GrantFiled: June 29, 2021Date of Patent: November 14, 2023Assignee: Amazon Technologies, Inc.Inventors: Zheng Tang, Lior Zamir, Prithviraj Banerjee, Manoj Aggarwal, Gerard Guy Medioni, Dilip Kumar
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Patent number: 11756036Abstract: Techniques for an identity-verification system to analyze image data representing palms of users using a segmented, characteristic-based approach. The system may compare palm-feature data representing characteristics of a palm of a user (or “query palm”) with stored palm-feature data of palms for user profiles (or “stored palms”). For instance, the system may identify characteristics of the query palm having salient or discriminative features, and compare palm-feature data for those discriminative characteristics to palm-feature data representing corresponding characteristics of stored palms of enrolled users. Additionally, the system may compare characteristics of the query palm with corresponding characteristics of stored palms until the system is confident that the query palm corresponds to a stored palm of a user profile.Type: GrantFiled: December 13, 2019Date of Patent: September 12, 2023Assignee: Amazon Technologies, Inc.Inventors: Manoj Aggarwal, Prithviraj Banerjee, Gerard Guy Medioni, Brad Musick
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Patent number: 11663805Abstract: This disclosure describes a user-recognition system that may perform one or more verification methods upon identifying a previous image that matches a current image of a palm of a user. For instance, the user-recognition system may perform the verification method(s) as part of the recognition method (e.g., after recognizing a matching image), in response to an audit process, in response to a request to re-analyze the image data (e.g., because a user indicates that he or she was not associated with a particular purchase or shopping session), and/or the like.Type: GrantFiled: March 23, 2021Date of Patent: May 30, 2023Assignee: Amazon Technologies, Inc.Inventors: Zheng Tang, Prithviraj Banerjee, Manoj Aggarwal, Gerard Guy Medioni
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Patent number: 11232294Abstract: Actors may be detected and tracked within a scene using multiple imaging devices provided in a network that are aligned with fields of view that overlap at least in part. Processors operating on the imaging devices may evaluate the images using one or more classifiers to recognize body parts within the images, and to associate the body parts with a common actor within the scene. Each of the imaging devices may generate records of the positions of the body parts and provide such records to a central server, that may correlate body parts appearing within images captured by two or more of the imaging devices and generate a three-dimensional model of an actor based on positions of the body parts. Motion of the body parts may be tracked in subsequent images, and the model of the actor may be updated based on the motion.Type: GrantFiled: September 27, 2017Date of Patent: January 25, 2022Assignee: Amazon Technologies, Inc.Inventors: Prithviraj Banerjee, Leonid Pishchulin, Jean Laurent Guigues, Gerard Guy Medioni
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Publication number: 20210097547Abstract: This disclosure describes techniques for providing instructions when receiving biometric data associated with a user. For instance, a user-recognition device may detect a portion of a user, such as a hand. The user-recognition device may then display a first graphical element indicating a target location for placing the portion of the user above the user-recognition device. Additionally, the user-recognition device may determine locations of the portion of the user above the user-recognition device. The user-recognition device may then display a second graphical element indicating the locations, such as when the locations are not proximate to the target location. Additionally, the user-recognition device may display instructions for moving the portion of the user to the target location. Based on detecting that the location of the portion of the user is proximate to the target location, the user-recognition device may send data representing the portion of the user to a remote system.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Inventors: Nichole Stockman, Korwin Jon Smith, Douglas Andrew Hungarter, Joshua Adam Cowan, Jared Corso, Rajeev Ranjan, Prithviraj Banerjee, Matthew Christopher Smith
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Patent number: 10586203Abstract: Described is a multiple-camera system and process for re-identifying a user located in a materials handling facility based on user patterns and/or descriptors representative of the user. In one implementation, a user pattern and/or a plurality of descriptors representative of a user are maintained as a position of a user is tracked through a materials handling facility. If the tracking of the user is lost, the last known position is stored with the user pattern and/or descriptors. If a new object is detected and confirmed to be a user, a user pattern and/or descriptors of the new object are compared with the stored user pattern and/or descriptors to determine if the new object is the user.Type: GrantFiled: March 25, 2015Date of Patent: March 10, 2020Assignee: Amazon Technologies, Inc.Inventors: Emilio Ian Maldonado, Pranab Mohanty, Ammar Chinoy, Joachim Sebastian Stahl, David Allen Smith, Prithviraj Banerjee
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Patent number: 9141359Abstract: A parallel-code optimization system includes a Procedural Concurrency Graph (PCG) generator. The PCG generator produces an initial PCG of a computer program including parallel code, and determines a refined PCG from the initial PCG by applying concurrency-type refinements and interference-type refinements to the initial PCG. The initial PCG and the refined PCG include nodes and edges connecting pairs of the nodes. The nodes represent defined procedures in the parallel code, and each edge represents a may-happen-in-parallel relation, and is associated with a set of lvalues that represents the immediate interference between the corresponding pair of nodes.Type: GrantFiled: December 13, 2010Date of Patent: September 22, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Pramod G. Joisha, Robert Samuel Schreiber, Prithviraj Banerjee, Hans Boehm, Dhruva R. Chakrabarti
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Publication number: 20150242802Abstract: The embodiments herein provide a method and system for presenting a sales pitch. The method comprises receiving information about a client from a plurality of sources, creating a client profile based on the received information about the client, training one or more sales personnel based on the client profile, generating one or more demonstrations of a sales pitch, wherein the one or more sales pitch is demonstrated by the sales personnel, posting the one or more generated demonstrations of the sales pitch to a server, verifying the one or more similar presentations having a favorable outcome and presenting the one or more posted presentations of the sales pitch by the sales personnel to the client, wherein the presentations are recorded in real-time, geo-stamped, and time-stamped.Type: ApplicationFiled: February 19, 2015Publication date: August 27, 2015Inventors: PRITHVIRAJ BANERJEE, GOPAL SWAMINATHAN
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Patent number: 8813054Abstract: A parallel-code optimization system includes a siloed program reference-identifier and an intermediate representation (IR) updater. The siloed program reference identifier determines siloed program references in parallel code, wherein siloed program references are free of cross-thread interference. The IR updater modifies data-flow abstractions based on the identified siloed program references.Type: GrantFiled: December 13, 2010Date of Patent: August 19, 2014Assignee: Hewlett-Packard Development Company, L. P.Inventors: Pramod G. Joisha, Robert Samuel Schreiber, Prithviraj Banerjee, Hans Boehm, Dhruva R. Chakrabarti
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Publication number: 20130205284Abstract: There is provided a computer-implemented method of performing ownership acquire policy selection. The method includes compiling an atomic section to generate an instrumented executable. The instrumented executable is configured to generate a runtime abort graph describing a plurality of computer memory accesses made by the instrumented executable. The method also includes selecting each of a plurality of policies based on the runtime abort graph. The plurality of policies include a first policy and a second policy. The first policy is different from the second policy. The method further includes compiling the atomic section to generate a modified executable. The modified executable is configured to perform the computer memory accesses according to the selected policies.Type: ApplicationFiled: February 2, 2012Publication date: August 8, 2013Inventors: Dhruva Chakrabarti, Prithviraj Banerjee, Hans Boehm, Pramod G. Joisha, Robert Schreiber
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Publication number: 20120151460Abstract: A parallel-code optimization system includes a Procedural Concurrency Graph (PCG) generator. The PCG generator produces an initial PCG of a computer program including parallel code, and determines a refined PCG from the initial PCG by applying concurrency-type refinements and interference-type refinements to the initial PCG. The initial PCG and the refined PCG include nodes and edges connecting pairs of the nodes. The nodes represent defined procedures in the parallel code, and each edge represents a may-happen-in-parallel relation, and is associated with a set of lvalues that represents the immediate interference between the corresponding pair of nodes.Type: ApplicationFiled: December 13, 2010Publication date: June 14, 2012Inventors: Pramod G. Joisha, Robert Samuel Schreiber, Prithviraj Banerjee, Hans Boehm, Dhruva Chakrabarti
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Publication number: 20120151462Abstract: A parallel-code optimization system includes a siloed program reference-identifier and an intermediate representation (IR) updater. The siloed program reference identifier determines siloed program references in parallel code, wherein siloed program references are free of cross-thread interference. The IR updater modifies data-flow abstractions based on the identified siloed program references.Type: ApplicationFiled: December 13, 2010Publication date: June 14, 2012Inventors: Pramod G. Joisha, Robert Samuel Schreiber, Prithviraj Banerjee, Hans Boehm, Dhruva R. Chakrabarti
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Patent number: 7376939Abstract: Electronic design automation tool specifies an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc.); specifies IP-cores and their interface; and understands IP-cores and functions via their interface. Further, techniques are provided for modeling the timing behavior of a function or functional block without drawing a timing diagram; understanding the interface behavior of a function block which captures the timing waveforms; specifying virtual functions which are built using basic functional units and their timing behavior; parsing and creating an internal graphical form for analyzing a specification for compilation; matching the components in the architecture specification and their instantiation to map the computations in the input graph produced from an application; and mapping the specification onto the target's components.Type: GrantFiled: February 7, 2002Date of Patent: May 20, 2008Assignee: Xilinx, Inc.Inventors: Anshuman Nayak, Malay Haldar, Alok Choudhary, Vikram Saxena, Prithviraj Banerjee
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Patent number: 7086040Abstract: A method for inferring the shape and dimension of arrays for high-level, array-based languages such as MATLAB is presented. The method uses the algebraic properties that underlie MATLAB's shape semantics and infers the shape that the program expression assumes. In one embodiment, a shape-tuple of the result of a program expression is inferred by creating a shape-tuple expression comprising the shape-tuples of the operands and the shape-tuple operator.Type: GrantFiled: January 30, 2001Date of Patent: August 1, 2006Assignee: Northwestern UniversityInventors: Pramod G. Joisha, Prithviraj Banerjee, Nagaraj Shenoy
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Patent number: 7000213Abstract: Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC or FPGA configuration. Intermediate transformations and optimizations are performed to obtain highly optimized description in RTL-VHDL or RTL Verilog of given MATLAB program. Optimizations include levelization, scalarization, pipelining, type-shape analysis, memory optimizations, precision analysis and scheduling.Type: GrantFiled: January 26, 2001Date of Patent: February 14, 2006Assignee: Northwestern UniversityInventors: Prithviraj Banerjee, Alok Choudhary, Malay Haldar, Anshuman Nayak
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Publication number: 20040019881Abstract: An improved method and process for array shape inferencing for high-level array-based languages such as MATLAB and APL. The process is based on a framework that algebraically describes the shape of an expression at compile time. The method leverages on algebraic properties that underlie MATLAB's shape semantics and exactly captures the shape that the expression assumes at run time. Other highlights of this method are its generality and the uniformity of its approach. Compared with the traditional shadow variable scheme, the algebraic view permits powerful shape-related assertions and optimizations not possible in the conventional approach.Type: ApplicationFiled: January 30, 2001Publication date: January 29, 2004Applicant: NORTHWESTERN UNIVERSITYInventors: Pramod G. Joisha, Prithviraj Banerjee, Nagaraj Shenoy
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Publication number: 20040019883Abstract: Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC or FPGA configuration. Intermediate transformations and optimizations are performed to obtain highly optimized description in RTL-VHDL or RTL Verilog of given MATLAB program. Optimizations include levelization, scalarization, pipelining, type-shape analysis, memory optimizations, precision analysis and scheduling.Type: ApplicationFiled: January 26, 2001Publication date: January 29, 2004Applicant: NORTHWESTERN UNIVERSITYInventors: Prithviraj Banerjee, Alok Choudhary, Malay Haldar, Anshuman Nayak