Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

Abstract: In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.

Abstract: In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.

Abstract: In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.

Abstract: In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.

Abstract: In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.

Abstract: An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.

Abstract: An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

Abstract: Embodiments herein relate to systems, apparatuses, processing, and techniques related to patterning one or more sides of a thin film capacitor (TFC) sheet, where the TFC sheet has a first side and a second side opposite the first side. The first side and the second side of the TFC sheet are metal and are separated by a dielectric layer, and the patterned TFC sheet is to provide at least one of a capacitor or a routing feature on a first side of a substrate that has the first side and a second side opposite the first side.

Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.

Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

Abstract: Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.

Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.

Abstract: An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.

Abstract: A package substrate is disclosed. The package substrate includes a substrate core, a cavity below the substrate core that extends from a surface of a first resist layer to a bottom surface of the package substrate, and a first terminal and a second terminal in the first resist layer. The package substrate also includes one or more passive components that are coupled inside the cavity to the first terminal and the second terminal.