Patents by Inventor Priya Ananthanarayanan
Priya Ananthanarayanan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8307236Abstract: In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.Type: GrantFiled: October 26, 2010Date of Patent: November 6, 2012Assignee: Apple Inc.Inventors: Sridhar P. Subramanian, Sukalpa Biswas, Vincent R. von Kaenel, Priya Ananthanarayanan
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Patent number: 8027213Abstract: A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to select a particular SRAM cell in response to a selection input. An oscillator circuit such as a ring oscillator, for example, on the integrated circuit may be configured to oscillate at a frequency that is dependent upon a read current of a selected SRAM cell during operation in a first mode. A frequency determining circuit that is coupled to the oscillator circuit may be configured to output a value corresponding to the frequency of oscillation of the oscillator circuit.Type: GrantFiled: June 19, 2009Date of Patent: September 27, 2011Assignee: Apple Inc.Inventors: Ashish R. Jain, Priya Ananthanarayanan, Greg M. Hess, Edgardo F. Klass
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Patent number: 7977998Abstract: An apparatus and method for testing level shifter threshold voltages on an integrated circuit includes one or more level shifter modules each including a number of level shifter circuits. Each level shifter circuit may be coupled to a first and a second voltage supply. Each level shifter circuit may also receive an input signal that is referenced to the first voltage supply, and to generate an output signal that is referenced to the second voltage supply. In addition, each level shifter module may include detection logic that may detect an output value of each of the level shifter circuits. The control circuit may be configured to iteratively change the voltage output from one of the voltage supplies, and maintaining a voltage on the other voltage supply while the input signal is provided to the level shifter circuits. The detection logic may capture the output value upon each change in voltage.Type: GrantFiled: June 9, 2009Date of Patent: July 12, 2011Assignee: Apple Inc.Inventors: Ashish R. Jain, Priya Ananthanarayanan, Edgardo F. Klass
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Publication number: 20110040998Abstract: In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.Type: ApplicationFiled: October 26, 2010Publication date: February 17, 2011Inventors: Sridhar P. Subramanian, Sukalpa Biswas, Vincent R. von Kaenel, Priya Ananthanarayanan
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Publication number: 20100322026Abstract: A mechanism for measuring the variability of the read current of SRAM cells on an integrated circuit includes the integrated circuit having an SRAM array including a plurality of SRAM cells. The integrated circuit may also include a selection circuit configured to select a particular SRAM cell in response to a selection input. An oscillator circuit such as a ring oscillator, for example, on the integrated circuit may be configured to oscillate at a frequency that is dependent upon a read current of a selected SRAM cell during operation in a first mode. A frequency determining circuit that is coupled to the oscillator circuit may be configured to output a value corresponding to the frequency of oscillation of the oscillator circuit.Type: ApplicationFiled: June 19, 2009Publication date: December 23, 2010Inventors: Ashish R. Jain, Priya Ananthanarayanan, Greg M. Hess, Edgardo F. Klass
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Publication number: 20100308887Abstract: An apparatus and method for testing level shifter threshold voltages on an integrated circuit includes one or more level shifter modules each including a number of level shifter circuits. Each level shifter circuit may be coupled to a first and a second voltage supply. Each level shifter circuit may also receive an input signal that is referenced to the first voltage supply, and to generate an output signal that is referenced to the second voltage supply. In addition, each level shifter module may include detection logic that may detect an output value of each of the level shifter circuits. The control circuit may be configured to iteratively change the voltage output from one of the voltage supplies, and maintaining a voltage on the other voltage supply while the input signal is provided to the level shifter circuits. The detection logic may capture the output value upon each change in voltage.Type: ApplicationFiled: June 9, 2009Publication date: December 9, 2010Inventors: Ashish R. Jain, Priya Ananthanarayanan, Edgardo F. Klass
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Patent number: 7836324Abstract: In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.Type: GrantFiled: April 26, 2007Date of Patent: November 16, 2010Assignee: Apple Inc.Inventors: Sridhar P. Subramanian, Sukalpa Biswas, Vincent R. von Kaenel, Priya Ananthanarayanan
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Publication number: 20080195884Abstract: In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.Type: ApplicationFiled: April 26, 2007Publication date: August 14, 2008Inventors: Sridhar P. Subramanian, Sukalpa Biswas, Vincent R. von Kaenel, Priya Ananthanarayanan
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Patent number: 7256617Abstract: A driver circuit that outputs a data signal uses feedback of the data signal to the driver circuit to modulate a drive strength of the driver circuit. The driver circuit has a pull-up driver stage and a pull-down driver stage. The pull-up driver stage uses a pull-up control circuit to modulate a drive strength of the pull-up driver stage dependent on a voltage of the data signal. The pull-down driver stage uses a pull-down control circuit to modulate a drive strength of the pull-down driver stage dependent on the voltage of the data signal.Type: GrantFiled: March 13, 2003Date of Patent: August 14, 2007Assignee: Sun Microsystems, Inc.Inventors: Priya Ananthanarayanan, Samudyatha Suryanarayana
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Patent number: 6859068Abstract: A self-correcting I/O interface driver scheme uses a delay difference detector to detect a difference in delays between an I/O data path and an I/O clock path. The delay difference detector inputs signals from a data output pin connected to the I/O data path and a clock output pin connected to the I/O clock path. Upon determining a delay difference between the signals from the data and clock output pins, the delay difference detector generates signals to one or more drivers in the I/O data path and the I/O clock path. These signals from the delay difference detector are used to effectively adjust delays of the one or more drivers in order to effectively reduce the delay difference between the I/O data path and the I/O clock path.Type: GrantFiled: August 8, 2003Date of Patent: February 22, 2005Assignee: Sun Microsystems, Inc.Inventors: Pradeep Trivedi, Priya Ananthanarayanan
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Publication number: 20050030064Abstract: A self-correcting I/O interface driver scheme uses a delay difference detector to detect a difference in delays between an I/O data path and an I/O clock path. The delay difference detector inputs signals from a data output pin connected to the I/O data path and a clock output pin connected to the I/O clock path. Upon determining a delay difference between the signals from the data and clock output pins, the delay difference detector generates signals to one or more drivers in the I/O data path and the I/O clock path. These signals from the delay difference detector are used to effectively adjust delays of the one or more drivers in order to effectively reduce the delay difference between the I/O data path and the I/O clock path.Type: ApplicationFiled: August 8, 2003Publication date: February 10, 2005Inventors: Pradeep Trivedi, Priya Ananthanarayanan
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Patent number: 6831487Abstract: A driver stage uses a primary driver and a secondary driver to balance drive current when transmitting a new data bit different than bits consecutively transmitted immediately previous to the new data bit. The primary driver activates one of a pull-down device and a pull-up device whenever transmitting a data bit. The secondary driver activates one of its pull-down device and a pull-up device when two or more consecutive are detected to be transmitted. In this case, current flow of the driver stage induced by the first of the consecutive bits is reduced by the secondary driver.Type: GrantFiled: March 20, 2003Date of Patent: December 14, 2004Assignee: Sun Microsystems, Inc.Inventors: Samudyatha Suryanarayana, Priya Ananthanarayanan
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Patent number: 6829548Abstract: An apparatus for measuring static phase error in a delay locked loop includes a first test stage and a second test stage. The first test stage receives a reference clock, a chip clock, and a control signal. In parallel with the first test stage, the second test stage receives the reference clock, the chip clock, and a complement of the control signal. Dependent on the control signal, the first test stage outputs a first test signal, and, dependent on the complement of the control signal, the second test stage outputs a second test signal. The first test signal and the second test signal are used to generate a set of static phase error measurements dependent on values of the control signal and the complement of the control signal. By averaging the set of static phase error measurements, a static phase error is measured for the delay locked loop.Type: GrantFiled: April 3, 2003Date of Patent: December 7, 2004Assignee: Sun Microsystems, Inc.Inventors: Priya Ananthanarayanan, Pradeep R. Trivedi, Claude R. Gauthier
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Publication number: 20040199345Abstract: An apparatus for measuring static phase error in a delay locked loop includes a first test stage and a second test stage. The first test stage receives a reference clock, a chip clock, and a control signal. In parallel with the first test stage, the second test stage receives the reference clock, the chip clock, and a complement of the control signal. Dependent on the control signal, the first test stage outputs a first test signal, and, dependent on the complement of the control signal, the second test stage outputs a second test signal. The first test signal and the second test signal are used to generate a set of static phase error measurements dependent on values of the control signal and the complement of the control signal. By averaging the set of static phase error measurements, a static phase error is measured for the delay locked loop.Type: ApplicationFiled: April 3, 2003Publication date: October 7, 2004Inventors: Priya Ananthanarayanan, Pradeep R. Trivedi, Claude R. Gauthier
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Publication number: 20040183573Abstract: A driver stage uses a primary driver and a secondary driver to balance drive current when transmitting a new data bit different than bits consecutively transmitted immediately previous to the new data bit. The primary driver activates one of a pull-down device and a pull-up device whenever transmitting a data bit. The secondary driver activates one of its pull-down device and a pull-up device when two or more consecutive are detected to be transmitted. In this case, current flow of the driver stage induced by the first of the consecutive bits is reduced by the secondary driver.Type: ApplicationFiled: March 20, 2003Publication date: September 23, 2004Inventors: Samudyatha Suryanarayana, Priya Ananthanarayanan
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Publication number: 20040178823Abstract: A driver circuit that outputs a data signal uses feedback of the data signal to the driver circuit to modulate a drive strength of the driver circuit. The driver circuit has a pull-up driver stage and a pull-down driver stage. The pull-up driver stage uses a pull-up control circuit to modulate a drive strength of the pull-up driver stage dependent on a voltage of the data signal. The pull-down driver stage uses a pull-down control circuit to modulate a drive strength of the pull-down driver stage dependent on the voltage of the data signal.Type: ApplicationFiled: March 13, 2003Publication date: September 16, 2004Inventors: Priya Ananthanarayanan, Samudyatha Suryanarayana
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Patent number: 6570409Abstract: A method and apparatus for performing logic operations using a current mode logic circuit is provided. Further, a method and apparatus for performing high fan-in logic operations is provided. Further, a logic circuit that selectively steers current based upon a plurality of inputs is provided. Further, a method for performing logic operations using current steering is provided.Type: GrantFiled: April 6, 2001Date of Patent: May 27, 2003Assignee: Sun Microsystems, Inc.Inventors: Priya Ananthanarayanan, Gajendra P. Singh
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Publication number: 20020145451Abstract: A method and apparatus for performing logic operations using a current mode logic circuit is provided. Further, a method and apparatus for performing high fan-in logic operations is provided. Further, a logic circuit that selectively steers current based upon a plurality of inputs is provided. Further, a method for performing logic operations using current steering is provided.Type: ApplicationFiled: April 6, 2001Publication date: October 10, 2002Inventors: Priya Ananthanarayanan, Gajendra P. Singh