Patents by Inventor Priya Darshini

Priya Darshini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220353687
    Abstract: A communication system is disclosed in which a base station apparatus obtains information identifying a total integrity protected uplink data rate for a user equipment (UE), allocates a portion of the total integrity protected uplink data rate to a secondary node (SN), and notifies the UE about the portion allocated to the SN.
    Type: Application
    Filed: March 24, 2020
    Publication date: November 3, 2022
    Applicant: NEC Corporation
    Inventors: Priya DARSHINI, Chadi KHIRALLAH, Sadafuku HAYASHI, Jagdeep Ahiuwaiia SINGH, Neeraj GUPTA
  • Patent number: 7260767
    Abstract: Methods for correcting errors in a GFP-T superblock include buffering the 64 bytes of data in an 8×8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In the first stage, the CRC remainder is compared to a single bit error syndrome table and if an error is located, it is corrected. In the second stage, the CRC remainder is compared to a double bit error syndrome table and if an error is located, it is corrected. The third stage corrects the second error of a double bit error. The flag byte is processed first, followed by the data bytes, eight bytes at a time.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: August 21, 2007
    Assignee: Transwitch Corporation
    Inventors: Santanu Bhattacharya, Neeraj Gupta, Yogesh Mittal, Priya Darshini, Arunava Dutta, Suvhasis Mukhopadhyay
  • Publication number: 20060041826
    Abstract: Methods for correcting errors in a GFP-T superblock include buffering the 64 bytes of data in an 8×8 byte buffer, buffering the flag byte in a separate buffer, calculating the CRC remainder, and performing single and double bit error correction in three stages. In the first stage, the CRC remainder is compared to a single bit error syndrome table and if an error is located, it is corrected. In the second stage, the CRC remainder is compared to a double bit error syndrome table and if an error is located, it is corrected. The third stage corrects the second error of a double bit error. The flag byte is processed first, followed by the data bytes, eight bytes at a time.
    Type: Application
    Filed: August 23, 2004
    Publication date: February 23, 2006
    Inventors: Santanu Bhattacharya, Neeraj Gupta, Yogesh Mittal, Priya Darshini, Arunava Dutta, Suvhasis Mukhopadhyay