Patents by Inventor Priya N. Vaidya
Priya N. Vaidya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9766672Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.Type: GrantFiled: March 19, 2013Date of Patent: September 19, 2017Assignee: Intel CorporationInventors: Bryan C. Morgan, Priya N. Vaidya, Premanand Sakarda, Marlon A. Moncrieffe
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Publication number: 20160378551Abstract: Systems and methods may provide for making a power efficiency determination at runtime based on one or more runtime usage notifications and scheduling a workload for execution on a hardware accelerator if the power efficiency determination indicates that execution of the workload on the hardware accelerator will be more efficient than execution of the workload on a host processor. Additionally, the workload may be scheduled for execution on the host processor if the power efficiency determination indicates that execution of the workload on the host processor will be more efficient than execution of the workload on the hardware accelerator. In one example, making the power efficiency determination includes applying one or more configurable rules to at least one of the one or more runtime usage notifications.Type: ApplicationFiled: June 24, 2015Publication date: December 29, 2016Applicant: Intel CorporationInventors: Priya N. Vaidya, Premanand Sakarda
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Publication number: 20140108830Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.Type: ApplicationFiled: March 19, 2013Publication date: April 17, 2014Inventors: Bryan C. Morgan, Priya N. Vaidya, Premanand Sakarda, Marlon A. Moncrieffe
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Patent number: 8402293Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.Type: GrantFiled: June 28, 2011Date of Patent: March 19, 2013Assignee: Intel CorporationInventors: Bryan C. Morgan, Priya N. Vaidya, Premanand Sakarda, Marlon A. Moncrieffe
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Publication number: 20120166844Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.Type: ApplicationFiled: June 28, 2011Publication date: June 28, 2012Inventors: BRYAN C. MORGAN, PRIYA N. VAIDYA, PREMANAND SAKARDA, MARLON A. MONCRIEFFE
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Patent number: 7971084Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.Type: GrantFiled: December 28, 2007Date of Patent: June 28, 2011Assignee: Intel CorporationInventors: Bryan C. Morgan, Priya N. Vaidya, Premanand Sakarda, Marlon A. Moncrieffe
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Patent number: 7814485Abstract: A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.Type: GrantFiled: December 7, 2004Date of Patent: October 12, 2010Assignee: Intel CorporationInventors: Bryan C Morgan, Premanand Sakarda, Priya N Vaidya, Yi Ge, Zhou Gao, Swee-chin Pang, Manoj I Thadani, Canhui Yuan
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Publication number: 20090172432Abstract: In one embodiment, an electronic apparatus comprises at least one processor and a computer readable medium coupled to the processor and comprising logic instructions encoded in the computer readable medium, wherein the instructions, when executed in a processing system, cause the processing system to perform operations comprising initializing a direct memory access profiler in an electronic system, wherein the direct memory access is coupled to a policy manager in the electronic system, measuring at least one memory consumption characteristic of the electronic system, communicating the at least one memory consumption characteristic to a policy manager of the electronic system, and using the at least one memory consumption characteristic to adjust a power state of the electronic system.Type: ApplicationFiled: December 28, 2007Publication date: July 2, 2009Inventors: Bryan C. Morgan, Priya N. Vaidya, Premanand Sakarda, Marlon A. Moncrieffe
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Patent number: 7346787Abstract: A disclosed method involves initializing a performance profiler of a processing system. The performance profiler may include performance profile parameters for a power management policy for the processing system. The method also involves retrieving performance metrics for the processing system from a performance monitoring unit (PMU) of the processing system, in response to a determination that performance details should be collected. A current performance state of the processing system may be determined, based at least in part on the performance profile parameters and the performance metrics from the PMU. The current performance state may then be communicated to a policy manager of the processing system. Other embodiments are disclosed and claimed.Type: GrantFiled: December 7, 2004Date of Patent: March 18, 2008Assignee: Intel CorporationInventors: Priya N Vaidya, Premanand Sakarda, Bryan C Morgan, Yi Ge
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Patent number: 7266646Abstract: A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be made to lock an optimal amount of functions that correspond to a given, limited amount of instruction cache.Type: GrantFiled: August 8, 2006Date of Patent: September 4, 2007Assignee: Marvell International Ltd.Inventors: Priya N. Vaidya, Moinul H. Khan
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Patent number: 7159096Abstract: A method and apparatus to perform memory management are described.Type: GrantFiled: March 31, 2004Date of Patent: January 2, 2007Assignee: Marvell International Ltd.Inventors: Moinul H. Khan, Priya N. Vaidya
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Publication number: 20030236810Abstract: A multiplication apparatus and system may include a multiplicand buffer to hold a digit of a multiplicand, a multiplier buffer to hold a digit of a multiplier, and a result buffer to hold a carry-free multiplied and accumulated result of the multiplicand and a plurality of reverse ordered digits included in the multiplier. An article, including a machine-accessible medium, may contain data capable of causing a machine to implement a multiplication method, including selecting a multiplicand plurality of digits, reversing the order of a selected multiplier plurality of digits to provide a reversed plurality of digits, and multiplying and accumulating the multiplicand plurality of digits and the reversed plurality of digits to provide a multiplication result.Type: ApplicationFiled: June 25, 2002Publication date: December 25, 2003Applicant: Intel CorporationInventors: Priya N. Vaidya, Minda Zhang
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Publication number: 20030059089Abstract: A row-wise technique may be utilized for determining a fractional matching block in a motion estimation vector algorithm. By interpolating and calculating a sum of absolute differences on a row-wise basis, a more efficient algorithm may be implemented. On a row-by-row basis, the corresponding interpolated values are updated and those values, once updated, may be compared to determine the best match among the potential fractional matching blocks. As a result, a fractional matching block may be identified to determine the motion vector to a greater degree of accuracy.Type: ApplicationFiled: September 25, 2001Publication date: March 27, 2003Inventors: James E. Quinlan, Priya N. Vaidya, Nigel Paver