Patents by Inventor Priya Selvaraj

Priya Selvaraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for checking operation of a mask generation algorithm
    Patent number: 7139997
    Abstract: Disclosed is a method for checking the operation of an IC mask generation algorithm in which at least a first identifier of the mask generation algorithm is associated with at least a first symbol that is not associated with generating a functional IC feature. The first symbol has a predetermined size and a predetermined shape. A predetermined location on a mask is also associated with the first symbol. A mask diagram on the mask is generated at least partially at the first predetermined location. The size and shape of the mask diagram is then compared with at least a portion of the first predetermined size and the first predetermined shape of the first symbol.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: November 21, 2006
    Assignee: Altera Corporation
    Inventors: Irfan Rahim, Bradley Jensen, Girish Venkitachalam, Hugh Sung-Ki O, Susan Falk, Priya Selvaraj
  • Polysilicon gate doping level variation for reduced leakage current
    Patent number: 7045427
    Abstract: A method for fabricating a transistor on a semiconductor substrate includes varying a polysilicon doping level near a first and second edge of a diffusion region with a polysilicon doping level of a center region of a polysilicon region.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: May 16, 2006
    Assignee: Altera Corporation
    Inventors: Peter McElheny, Priya Selvaraj, Yow-Juang (Bill) Liu, Francois Gregoire
  • Polysilicon gate doping level variation for reduced leakage current
    Publication number: 20050003601
    Abstract: A method for fabricating a transistor on a semiconductor substrate includes varying a polysilicon doping level near a first and second edge of a diffusion region with a polysilicon doping level of a center region of a polysilicon region.
    Type: Application
    Filed: April 22, 2004
    Publication date: January 6, 2005
    Inventors: Peter McElheny, Priya Selvaraj, Yow-Juang Liu, Francois Gregoire
  • Polysilicon gate doping level variation for reduced leakage current
    Patent number: 6750106
    Abstract: A method of fabricating transistors on a semiconductor substrate is disclosed according to a first embodiment of the present invention. Gate dielectrics of equal thickness are provided to a first and second transistor on the semiconductor substrate. A polysilicon doping level of the first transistor is varied with a polysilicon doping level of the second transistor.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: June 15, 2004
    Assignee: Altera Corporation
    Inventors: Peter McElheny, Priya Selvaraj, Bill Liu, Francois Gregoire
  • POLYSILICON GATE DOPING LEVEL VARIATION FOR REDUCED LEAKAGE CURRENT
    Publication number: 20040097043
    Abstract: A method of fabricating transistors on a semiconductor substrate is disclosed according to a first embodiment of the present invention. Gate dielectrics of equal thickness are provided to a first and second transistor on the semiconductor substrate. A polysilicon doping level of the first transistor is varied with a polysilicon doping level of the second transistor.
    Type: Application
    Filed: May 28, 2002
    Publication date: May 20, 2004
    Inventors: Peter McElheny, Priya Selvaraj, Bill Liu, Francois Gregoire