Abstract: A 3D IC device includes a first device tier including a first set of active devices, a second device tier including a second set of active devices, and a clock distribution network including clock signal routing interconnects arranged in an interconnect structure arranged at a side of the first device tier facing the second device tier. The device includes a logic circuit including registers each including a first active device arranged along a data path of the register and a second active device arranged along a clock path of the register. The first active device is included in the first set of active devices of the first device tier and the second active device is included in the second set of active devices of the second device tier and connected to the clock distribution network to receive a clock signal.

Abstract: A device includes a first device tier including a first set of active devices and a second device tier including a second set of active devices. The device also includes a clocked circuit including first active devices of the first set of active devices, and a clock distribution network including a plurality of clock signal routing interconnects arranged in an interconnect structure arranged at a side of the first device tier facing the second device tier. The device also includes a set of active clock devices formed by second active devices of the second set of active devices. The clocked circuit is connected to the clock distribution network to receive a clock signal.