Abstract: This application discloses an electronic design automation tool configured to perform one or more static reset checks on reset functionality in a circuit design. The electronic design automation tool can detect the reset functionality in the circuit design, identify a portion of the circuit design having a set of resettable components, and determine whether the portion of the circuit design includes a reset design error based, at least in part, on the reset functionality in the circuit design. The static reset checks can include a domain congruency check, a reset skew check, and a glitch detection check, each of which can identify different design errors that may cause reset functionality in the circuit design to operate improperly.

Abstract: This application discloses an electronic design automation tool configured to perform one or more static reset checks on reset functionality in a circuit design. The electronic design automation tool can detect the reset functionality in the circuit design, identify a portion of the circuit design having a set of resettable components, and determine whether the portion of the circuit design includes a reset design error based, at least in part, on the reset functionality in the circuit design. The static reset checks can include a domain congruency check, a reset skew check, and a glitch detection check, each of which can identify different design errors that may cause reset functionality in the circuit design to operate improperly.

Abstract: The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation.

Abstract: The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation.

Abstract: The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation.