Patents by Inventor Priyadarshi Panda

Priyadarshi Panda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230305531
    Abstract: A cool cluster comprises one or more transfer chambers; a plurality of process chambers connected to the one or more transfer chambers; and a computing device of the tool cluster. The computing device is to receive first measurements generated by sensors of a first process chamber during or after a process is performed within the first process chamber; determine that the first process chamber is due for maintenance based on processing the first measurements using a first trained machine learning model; after maintenance has been performed on the first process chamber, receive second measurements generated by the sensors during or after a seasoning process is performed within the first process chamber; and determine that the first process chamber is ready to be brought back into service based on processing the second measurements using a second trained machine learning model.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 28, 2023
    Inventors: Priyadarshi Panda, Lei Lian, Pengyu Han, Todd J. Egan, Prashant Aji, Eli Mor, Alex J. Tom, Leonard Michael Tedeschi
  • Patent number: 11751382
    Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: September 5, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Lequn Liu, Priyadarshi Panda, Jonathan C. Shaw
  • Patent number: 11709477
    Abstract: A substrate processing system comprises one or more transfer chambers; a plurality of process chambers connected to the one or more transfer chambers; and a computing device connected to each of the plurality of process chambers. The computing device is to receive first measurements generated by sensors of a first process chamber during or after a process is performed within the first process chamber; determine that the first process chamber is due for maintenance based on processing the first measurements using a first trained machine learning model; after maintenance has been performed on the first process chamber, receive second measurements generated by the sensors during or after a seasoning process is performed within the first process chamber; and determine that the first process chamber is ready to be brought back into service based on processing the second measurements using a second trained machine learning model.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: July 25, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Priyadarshi Panda, Lei Lian, Pengyu Han, Todd J. Egan, Prashant Aji, Eli Mor, Alex J. Tom, Leonard Michael Tedeschi
  • Patent number: 11658043
    Abstract: A method of patterning a substrate is provided. The method includes modifying a surface of a metal-containing layer formed over a substrate positioned in a processing region of a processing chamber by exposing the surface of the metal-containing layer to plasma effluents of a chlorine-containing gas precursor and an oxygen-containing gas precursor to form a modified surface of the metal-containing layer. The method further includes directing plasma effluents of an inert gas precursor towards the modified surface of the metal-containing layer. The plasma effluents of the inert gas precursor are directed by applying a bias voltage to a substrate support holding the substrate. The method further includes anisotropically etching the modified surface of the metal-containing layer with the plasma effluents of the inert gas precursor to form a first recess having a first sidewall in the metal-containing layer.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: May 23, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jonathan Shaw, Priyadarshi Panda, Nancy Fung, Yongchang Dong, Somaye Rasouli, Gene Lee
  • Patent number: 11631680
    Abstract: A process of smoothing a top surface of a bit line metal of a memory structure to decrease resistance of a bit line stack. The process includes depositing titanium layer of approximately 30 angstroms to 50 angstroms on polysilicon layer on a substrate, depositing first titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on titanium layer, annealing substrate at a temperature of approximately 700 degrees Celsius to approximately 850 degrees Celsius, depositing second titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on first titanium nitride layer after annealing, depositing a bit line metal layer of ruthenium on second titanium nitride layer, annealing bit line metal layer at temperature of approximately 550 degrees Celsius to approximately 650 degrees Celsius, and soaking bit line metal layer in hydrogen-based ambient for approximately 3 minutes to approximately 6 minutes during annealing.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: April 18, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Priyadarshi Panda, In Seok Hwang
  • Patent number: 11621266
    Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: April 4, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
  • Publication number: 20220238533
    Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Lequn Liu, Priyadarshi Panda, Jonathan C. Shaw
  • Publication number: 20220214662
    Abstract: A substrate processing system comprises one or more transfer chambers; a plurality of process chambers connected to the one or more transfer chambers; and a computing device connected to each of the plurality of process chambers. The computing device is to receive first measurements generated by sensors of a first process chamber during or after a process is performed within the first process chamber; determine that the first process chamber is due for maintenance based on processing the first measurements using a first trained machine learning model; after maintenance has been performed on the first process chamber, receive second measurements generated by the sensors during or after a seasoning process is performed within the first process chamber; and determine that the first process chamber is ready to be brought back into service based on processing the second measurements using a second trained machine learning model.
    Type: Application
    Filed: January 6, 2021
    Publication date: July 7, 2022
    Inventors: Priyadarshi Panda, Lei Lian, Pengyu Han, Todd J. Egan, Prashant Aji, Eli Mor, Alex J. Tom, Leonard Michael Tedeschi
  • Publication number: 20220165593
    Abstract: A method of forming a multi-layer stack on a substrate comprises: processing a substrate in a first process chamber using a first deposition process to deposit a first layer of a multi-layer stack on the substrate; removing the substrate from the first process chamber; measuring a first thickness of the first layer using an optical sensor; determining, based on the first thickness of the first layer, a target second thickness for a second layer of the multi-layer stack; determining one or more process parameter values for a second deposition process that will achieve the second target thickness for the second layer; and processing the substrate in a second process chamber using the second deposition process with the one or more process parameter values to deposit the second layer of the multi-layer stack approximately having the target second thickness over the first layer.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Inventors: Priyadarshi Panda, Lei Lian, Leonard Michael Tedeschi
  • Publication number: 20220165541
    Abstract: A substrate processing system comprises an etch chamber configured to perform an etch process on a substrate, the etch chamber comprising an optical sensor to generate one or more optical measurements of a film on the substrate during and/or after the etch process. The system further comprises a computing device operatively connected to the etch chamber, wherein the computing device is to: receive the one or more optical measurements of the film; determine, for each optical measurement of the one or more optical measurements, a film thickness of the film; determine an etch rate of the film based on the one or more optical measurements using the determined film thickness of each optical measurement of the one or more optical measurements; and determine a process parameter value of at least one process parameter for a previously performed process that was performed on the substrate based on the etch rate.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Inventors: Priyadarshi Panda, Lei Lian, Leonard Michael Tedeschi
  • Patent number: 11329052
    Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 10, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Lequn Liu, Priyadarshi Panda, Jonathan C. Shaw
  • Publication number: 20220068935
    Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
    Type: Application
    Filed: November 9, 2021
    Publication date: March 3, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
  • Publication number: 20220068661
    Abstract: A method of patterning a substrate is provided. The method includes modifying a surface of a metal-containing layer formed over a substrate positioned in a processing region of a processing chamber by exposing the surface of the metal-containing layer to plasma effluents of a chlorine-containing gas precursor and an oxygen-containing gas precursor to form a modified surface of the metal-containing layer. The method further includes directing plasma effluents of an inert gas precursor towards the modified surface of the metal-containing layer. The plasma effluents of the inert gas precursor are directed by applying a bias voltage to a substrate support holding the substrate. The method further includes anisotropically etching the modified surface of the metal-containing layer with the plasma effluents of the inert gas precursor to form a first recess having a first sidewall in the metal-containing layer.
    Type: Application
    Filed: July 29, 2021
    Publication date: March 3, 2022
    Inventors: Jonathan SHAW, Priyadarshi PANDA, Nancy FUNG, Yongchang DONG, Somaye RASOULI, Gene LEE
  • Patent number: 11171141
    Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: November 9, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
  • Publication number: 20210066309
    Abstract: A process of smoothing a top surface of a bit line metal of a memory structure to decrease resistance of a bit line stack. The process includes depositing titanium layer of approximately 30 angstroms to 50 angstroms on polysilicon layer on a substrate, depositing first titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on titanium layer, annealing substrate at a temperature of approximately 700 degrees Celsius to approximately 850 degrees Celsius, depositing second titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on first titanium nitride layer after annealing, depositing a bit line metal layer of ruthenium on second titanium nitride layer, annealing bit line metal layer at temperature of approximately 550 degrees to approximately 650 degrees, and soaking bit line metal layer in hydrogen-based ambient for approximately 3 minutes to approximately 6 minutes during annealing.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 4, 2021
    Inventors: Priyadarshi PANDA, In Seok HWANG
  • Publication number: 20210035982
    Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.
    Type: Application
    Filed: July 27, 2020
    Publication date: February 4, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Lequn Liu, Priyadarshi Panda, Jonathan C. Shaw
  • Patent number: 10903112
    Abstract: A process of smoothing a top surface of a bit line metal of a memory structure decreases resistance of a bit line stack. The process includes depositing a titanium layer of approximately 30 angstroms to 50 angstroms on a polysilicon layer on a substrate, depositing a first titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on the titanium layer, annealing the substrate at a temperature of approximately 700 degrees Celsius to approximately 850 degrees Celsius, depositing a second titanium nitride layer of approximately 15 angstroms to approximately 40 angstroms on the first titanium nitride layer after annealing, and depositing a bit line metal layer of ruthenium on the second titanium nitride layer.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: January 26, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Priyadarshi Panda, Jianxin Lei, Sanjay Natarajan, In Seok Hwang, Nobuyuki Sasaki
  • Publication number: 20200286897
    Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 10, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Priyadarshi Panda, Seshadri Ganguli, Sang Ho Yu, Sung-Kwan Kang, Gill Yong Lee, Sanjay Natarajan, Rajib Lochan Swain, Jorge Pablo Fernandez
  • Publication number: 20200235104
    Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Priyadarshi Panda, Jianxin Lei, Wenting Hou, Mihaela Balseanu, Ning Li, Sanjay Natarajan, Gill Yong Lee, In Seok Hwang, Nobuyuki Sasaki, Sung-Kwan Kang
  • Patent number: 10718101
    Abstract: A system of generating water from the air in the most energy efficient manner is provided. The water generating apparatus uses a combination of rotating pre-loader wheels of separation materials, mechanical condensation system such as Vapor Compression Cycle (VCC), filtration and mineral addition units to create an energy efficient system for generating water from ambient air. An IoT water generating apparatus optimized through systems integration including smart controls and programming board for optimizing water production using weather and utility data for energy efficient water production from ambient air.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: July 21, 2020
    Inventors: Priyadarshi Panda, Chaitanya Sharma