Patents by Inventor Priyal Shah
Priyal Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11911839Abstract: A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.Type: GrantFiled: December 28, 2021Date of Patent: February 27, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Priyal Shah, Rahul Agarwal, Raja Swaminathan, Brett P. Wilkerson
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Patent number: 11810891Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.Type: GrantFiled: March 2, 2021Date of Patent: November 7, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Priyal Shah, Milind S. Bhagavat
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Patent number: 11742301Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.Type: GrantFiled: August 19, 2019Date of Patent: August 29, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Rahul Agarwal, Milind S. Bhagavat, Priyal Shah, Chia-Hao Cheng, Brett P. Wilkerson, Lei Fu
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Publication number: 20230201952Abstract: A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Inventors: PRIYAL SHAH, RAHUL AGARWAL, RAJA SWAMINATHAN, BRETT P. WILKERSON
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Patent number: 11676924Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.Type: GrantFiled: March 8, 2021Date of Patent: June 13, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Priyal Shah, Milind S. Bhagavat, Lei Fu
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Publication number: 20230093924Abstract: A semiconductor package includes a substrate having opposing first and second surfaces as well as a semiconductor chip component disposed at the second surface and having third and fourth opposing surfaces. A package lid structure is affixed to the second surface of the substrate and the fourth surface of the semiconductor chip component, and has a planar component overlying the semiconductor chip component and having a fifth surface facing the fourth surface and an opposing sixth surface. The planar component includes an aperture extending between the fifth surface and the sixth surface so as to expose at least a portion of the fourth surface of the semiconductor chip component. A thermal exchange structure can be mounted on the package lid structure to form a thermal extraction pathway with the semiconductor die component via the aperture, either directly or via an interposing thermally conductive plate.Type: ApplicationFiled: September 30, 2021Publication date: March 30, 2023Inventors: Priyal Shah, Brett P. Wilkerson, Raja Swaminathan
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Publication number: 20220319871Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.Type: ApplicationFiled: June 17, 2022Publication date: October 6, 2022Inventors: PRIYAL SHAH, MILIND S. BHAGAVAT, BRETT P. WILKERSON, LEI FU, RAHUL AGARWAL
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Publication number: 20220199429Abstract: Structural thermal interfacing for lidded semiconductor packages, including: applying, to a periphery of a surface of a chip, a stiffening adhesive framing a center portion of the chip; applying, to the center portion of the chip, a thermal interface material; and applying a lid to the chip, wherein the lid contacts the stiffening adhesive and is thermally coupled to the chip via the thermal interface material after application to the chip.Type: ApplicationFiled: December 17, 2021Publication date: June 23, 2022Inventors: PRIYAL SHAH, RAJA SWAMINATHAN, BRETT P. WILKERSON
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Patent number: 11367628Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.Type: GrantFiled: July 16, 2019Date of Patent: June 21, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Priyal Shah, Milind S. Bhagavat, Brett P. Wilkerson, Lei Fu, Rahul Agarwal
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Publication number: 20210296194Abstract: Various molded semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a routing substrate and a semiconductor chip mounted on and electrically connected to the routing substrate. The semiconductor chip has plural side surfaces. A molding layer at least partially encases the semiconductor chip. The molding layer has a tread and a riser, the riser abutting at least some of the side surfaces.Type: ApplicationFiled: March 18, 2020Publication date: September 23, 2021Inventors: Priyal Shah, Rahul Agarwal, Milind S. Bhagavat, Chia-Hao Cheng
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Publication number: 20210193604Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.Type: ApplicationFiled: March 8, 2021Publication date: June 24, 2021Inventors: PRIYAL SHAH, MILIND S. BHAGAVAT, LEI FU
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Publication number: 20210183810Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.Type: ApplicationFiled: March 2, 2021Publication date: June 17, 2021Inventors: PRIYAL SHAH, MILIND S. BHAGAVAT
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Patent number: 10943880Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.Type: GrantFiled: May 16, 2019Date of Patent: March 9, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Priyal Shah, Milind S. Bhagavat, Lei Fu
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Patent number: 10937755Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.Type: GrantFiled: June 29, 2018Date of Patent: March 2, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Priyal Shah, Milind S. Bhagavat
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Publication number: 20210057352Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.Type: ApplicationFiled: August 19, 2019Publication date: February 25, 2021Inventors: Rahul Agarwal, Milind S. Bhagavat, Priyal Shah, Chia-Hao Cheng, Brett P. Wilkerson, Lei Fu
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Publication number: 20210020459Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.Type: ApplicationFiled: July 16, 2019Publication date: January 21, 2021Inventors: Priyal Shah, Milind S. Bhagavat, Brett P. Wilkerson, Lei Fu, Rahul Agarwal
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Publication number: 20200365543Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.Type: ApplicationFiled: May 16, 2019Publication date: November 19, 2020Inventors: Priyal Shah, Milind S. Bhagavat, Lei Fu
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Patent number: 10593620Abstract: Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer (RDL) structure. The RDL structure includes plural metallization layers and plural polymer layers. One of the polymer layers is positioned over one of the metallization layers. The one of the metallization layers has conductor traces. The one of the polymer layers has an upper surface that is substantially planar at least where the conductor traces are positioned. A semiconductor chip is positioned on and electrically connected to the RDL structure. A molding layer is positioned on the RDL structure and at least partially encases the semiconductor chip.Type: GrantFiled: April 27, 2018Date of Patent: March 17, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Rahul Agarwal, Milind S. Bhagavat, Priyal Shah
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Publication number: 20200006280Abstract: Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Priyal Shah, Milind S. Bhagavat
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Publication number: 20190333851Abstract: Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer (RDL) structure. The RDL structure includes plural metallization layers and plural polymer layers. One of the polymer layers is positioned over one of the metallization layers. The one of the metallization layers has conductor traces. The one of the polymer layers has an upper surface that is substantially planar at least where the conductor traces are positioned. A semiconductor chip is positioned on and electrically connected to the RDL structure. A molding layer is positioned on the RDL structure and at least partially encases the semiconductor chip.Type: ApplicationFiled: April 27, 2018Publication date: October 31, 2019Inventors: Rahul Agarwal, Milind S. Bhagavat, Priyal Shah