Patents by Inventor Priyanka Dasgupta

Priyanka Dasgupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200334580
    Abstract: Various embodiments are provided for implementing intelligent decision support system in a computing environment by a processor. Data of historical decisions may be collected and examples of decisions by domain experts may be generated. One or more machine learning models may be generated using different splits of the historical data and the annotated data. The one or more machine learning models may be combined and used to generate ensemble machine learning models that generate recommendations for the decisions. Users interact with a user interface displaying the data, recommendations, reasons for recommendations and a conversational dialog system for querying about the data, recommendations and guidance for decision making.
    Type: Application
    Filed: April 17, 2019
    Publication date: October 22, 2020
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anshul SHEOPURI, Binny Rieder, Pooja ARYA, Nickle LAMOREAUX, Joanna DALY, Saikat MUKHOPADHYAY, Priyanka DASGUPTA, Nandakishore KAMBHATLA, Aditya TELANG, Priyanka AGRAWAL
  • Patent number: 10740515
    Abstract: Systems, methods, media, and other such embodiments described herein relate to insertion of test points in circuit design and associated test coverage for a circuit design. One embodiment involves a circuit design with a plurality of circuit elements and a plurality of clock gating logic elements. A first node coupled to a first circuit element is selected for insertion of a test point circuit element. Elements of the design are identified that contribute to a data state of the first node, and clock elements for these identified design elements are traced. An ungated clock input node from this trace is selected, and the clock input from this node is connected to the test point circuit element. The circuit design is then updated with this connection. In various embodiments when multiple ungated clock input nodes are identified by the trace, additional criteria are used to select among the ungated clock input nodes.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 11, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jagjot Kaur, Priyanka Dasgupta, Vivek Chickermane, Gopi Kudva
  • Patent number: 10417363
    Abstract: Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: September 17, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Jagjot Kaur, Priyanka Dasgupta, Pratyush Aditya Kothamasu, Vivek Chickermane