Patents by Inventor Priyatharshan Pathmanathan

Priyatharshan Pathmanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuits and methods providing electronic band gap (EBG) structures at memory module electrical coupling
    Patent number: 10349513
    Abstract: A system includes: a printed circuit board having a plurality of conductive traces; a processing device coupled to the printed circuit board and in electrical communication with the plurality of conductive traces; a first memory module and a second memory module in electrical communication with the plurality of conductive traces and sharing channels of the conductive traces, wherein the first memory module is physically more proximate to the processing device than is the second memory module; and an electronic band gap (EBG) structure physically disposed in an area between the first memory module and the second memory module.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Priyatharshan Pathmanathan
  • CIRCUITS AND METHODS PROVIDING ELECTRONIC BAND GAP (EBG) STRUCTURES AT MEMORY MODULE ELECTRICAL COUPLING
    Publication number: 20180035533
    Abstract: A system includes: a printed circuit board having a plurality of conductive traces; a processing device coupled to the printed circuit board and in electrical communication with the plurality of conductive traces; a first memory module and a second memory module in electrical communication with the plurality of conductive traces and sharing channels of the conductive traces, wherein the first memory module is physically more proximate to the processing device than is the second memory module; and an electronic band gap (EBG) structure physically disposed in an area between the first memory module and the second memory module.
    Type: Application
    Filed: July 25, 2017
    Publication date: February 1, 2018
    Inventor: Priyatharshan Pathmanathan
  • Circuits and methods providing mutual capacitance in vertical electrical connections
    Patent number: 9722012
    Abstract: An electrical device including a structure having a plurality of dielectric layers, the structure further having a plurality of vertical electrical connections extending from a top layer of the dielectric layers to a bottom layer of the dielectric layers, a first vertical electrical connection of the plurality of vertical electrical connections including a first capacitive structure that extends in a plane perpendicular to a vertical dimension of the vertical electrical connection, wherein the first capacitive structure is disposed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below the top layer, and a second vertical electrical connection of the plurality of vertical electrical connections including a second capacitive structure extending in the plane and disposed on the first dielectric layer.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: August 1, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Priyatharshan Pathmanathan, Devarshi Patel, Dennis Allen Northgrave, Kyle Roberts
  • Highly coupled spiral planar inductors structure at bump to compensate on die excess capacitance of differential I/O
    Patent number: 9214426
    Abstract: Methods and apparatuses for reducing excess on die capacitance. The method couples a first die pad to a first via. The method couples a second die pad to a second via. The method couples a first inductor to the first die pad and the second via. The method couples a second inductor to the second die pad and the first via.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: December 15, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Siamak Fazelpour, Priyatharshan Pathmanathan, John Stephen Loffink