Patents by Inventor Priyesh Kumar
Priyesh Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10025573Abstract: Methods and systems to install a player to process content data are disclosed. In some embodiments, a method includes launching a content access manager on a user device to read metadata containing compatible player data, determine whether a compatible player able to access the content data is installed on the user device, and if not, to install a compatible player. Other embodiments involve receiving content data and data about one or more compatible players able to access the content data, generating the metadata using the data about one or more compatible players, and distributing the content data, the metadata, and the content access manager in a transmittable unit. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: April 8, 2009Date of Patent: July 17, 2018Assignee: Adobe Systems IncorporatedInventors: Thangaraj Umapathy, Richard Teo, Sudharshan Somasundaram, Kapil Raja Durga, Akshava G, Raghuram C G, Shyam Rajagopalan, Mihir Gore, Mandeep Singh, Hemantha Sharma, Priyesh Kumar
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Patent number: 8898527Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises at least one clock module comprising one or more clock dividers and associated clock divider logic, and the scan test circuitry is configured to permit testing of at least a portion of the clock divider logic. A given scan chain of the scan test circuitry may comprise first and second scan cells, with the first scan cell having a scan output coupled to a scan input of the second scan cell, and the second scan cell having a data input driven by an output of the clock divider logic.Type: GrantFiled: January 18, 2013Date of Patent: November 25, 2014Assignee: LSI CorporationInventors: Priyesh Kumar, Komal N. Shah, Ramesh C. Tekumalla
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Patent number: 8812921Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of sub-chains associated with respective distinct clock domains, and clock domain bypass circuitry configured to selectively bypass one or more of the sub-chains. The scan chain is configurable in a scan shift mode of operation to form a serial shift register that includes fewer than all of the sub-chains with at least a remaining one of the sub-chains being bypassed by the clock domain bypass circuitry so as to not be part of the serial shift register in the scan shift mode. By selectively bypassing portions of the scan chain associated with particular clock domains, the clock domain bypass circuitry serves to reduce test time and power consumption during scan testing.Type: GrantFiled: October 25, 2011Date of Patent: August 19, 2014Assignee: LSI CorporationInventors: Ramesh C. Tekumalla, Priyesh Kumar
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Publication number: 20140208175Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises at least one clock module comprising one or more clock dividers and associated clock divider logic, and the scan test circuitry is configured to permit testing of at least a portion of the clock divider logic. A given scan chain of the scan test circuitry may comprise first and second scan cells, with the first scan cell having a scan output coupled to a scan input of the second scan cell, and the second scan cell having a data input driven by an output of the clock divider logic.Type: ApplicationFiled: January 18, 2013Publication date: July 24, 2014Applicant: LSI CorporationInventors: Priyesh Kumar, Komal N. Shah, Ramesh C. Tekumalla
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Publication number: 20140201584Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells. The scan test circuitry further comprises control circuitry configured to control selective application of at least a particular one of a plurality of reset signals to reset inputs of at least a subset of the scan cells of the scan chain. For example, the control circuitry may comprise a first reset multiplexer configured to select between a first functional mode reset signal and a first scan mode reset signal for application to reset inputs of respective scan cells of the scan chain, and an additional multiplexer configured to select between an additional functional mode reset signal and an additional scan mode reset signal for application to reset inputs of respective internal flip-flops of the additional circuitry.Type: ApplicationFiled: January 17, 2013Publication date: July 17, 2014Applicant: LSI CorporationInventors: Ramesh C. Tekumalla, Priyesh Kumar, Prakash Krishnamoorthy
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Patent number: 8738978Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, including at least one wrapper cell scan chain arranged between first and second circuitry cores of the additional circuitry, with the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation. At least one of the wrapper cells of the wrapper cell scan chain comprises a flip-flop having a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores. In an HDD controller embodiment, the first and second circuitry cores may comprise respective read channel and additional cores of a system-on-chip.Type: GrantFiled: June 30, 2011Date of Patent: May 27, 2014Assignee: LSI CorporationInventors: Ramesh C. Tekumalla, Partho Tapan Chaudhuri, Priyesh Kumar, Komal N. Shah
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Publication number: 20140033198Abstract: Methods and systems to install a player to process content data are disclosed. In some embodiments, a method includes launching a content access manager on a user device to read metadata containing compatible player data, determine whether a compatible player able to access the content data is installed on the user device, and if not, to install a compatible player. Other embodiments involve receiving content data and data about one or more compatible players able to access the content data, generating the metadata using the data about one or more compatible players, and distributing the content data, the metadata, and the content access manager in a transmittable unit. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: April 8, 2009Publication date: January 30, 2014Applicant: Adobe Systems IncorporatedInventors: Thangaraj Umapathy, Richard Teo, Sudharshan Somasundaram, Kapil Raja Durga, Akshaya G, Raghuram CG, Shyam Rajagopalan, Mihir Gore, Mandeep Singh, Hemantha Sharma, Priyesh Kumar
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Publication number: 20130311843Abstract: An integrated circuit comprises a memory or other circuit core having an input interface and an output interface, scan circuitry comprising at least one scan chain having a plurality of scan cells, and additional circuitry associated with at least one of the input interface and the output interface and testable utilizing said at least one scan chain. The scan circuitry further comprises a scan controller configured to control signal values applied to one or more signal lines of the input interface in conjunction with testing of the additional circuitry utilizing said at least one scan chain. For example, the scan controller may control signal values applied to respective address input and write enable signal lines in a manner that ensures that data written to a memory in a write operation of a given memory cycle can be read from the memory in a read operation of a subsequent memory cycle.Type: ApplicationFiled: May 16, 2012Publication date: November 21, 2013Applicant: LSI CorporationInventors: Ramesh C. Tekumalla, Priyesh Kumar
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Patent number: 8566658Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of the scan chain comprises output control circuitry which is configured to disable a functional data output of the scan cell in the scan shift mode of operation and to disable a scan output of the scan cell in the functional mode of operation.Type: GrantFiled: August 24, 2011Date of Patent: October 22, 2013Assignee: LSI CorporationInventors: Ramesh C. Tekumalla, Priyesh Kumar, Prakash Krishnamoorthy, Parag Madhani
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Publication number: 20130103994Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of sub-chains associated with respective distinct clock domains, and clock domain bypass circuitry configured to selectively bypass one or more of the sub-chains. The scan chain is configurable in a scan shift mode of operation to form a serial shift register that includes fewer than all of the sub-chains with at least a remaining one of the sub-chains being bypassed by the clock domain bypass circuitry so as to not be part of the serial shift register in the scan shift mode. By selectively bypassing portions of the scan chain associated with particular clock domains, the clock domain bypass circuitry serves to reduce test time and power consumption during scan testing.Type: ApplicationFiled: October 25, 2011Publication date: April 25, 2013Applicant: LSI CorporationInventors: Ramesh C. Tekumalla, Priyesh Kumar
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Publication number: 20130007547Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, including at least one wrapper cell scan chain arranged between first and second circuitry cores of the additional circuitry, with the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation. At least one of the wrapper cells of the wrapper cell scan chain comprises a flip-flop having a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores. In an HDD controller embodiment, the first and second circuitry cores may comprise respective read channel and additional cores of a system-on-chip.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Inventors: Ramesh C. Tekumalla, Partho Tapan Chaudhuri, Priyesh Kumar, Komal N. Shah
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Publication number: 20120246529Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of the scan chain comprises output control circuitry which is configured to disable a functional data output of the scan cell in the scan shift mode of operation and to disable a scan output of the scan cell in the functional mode of operation.Type: ApplicationFiled: August 24, 2011Publication date: September 27, 2012Inventors: Ramesh C. Tekumalla, Priyesh Kumar, Prakash Krishnamoorthy, Parag Madhani