Abstract: In accordance with the principles herein, a co-design approach for compute-in-memory inference for deep neural networks (DNN) is set forth. Multiplication-free function approximators are employed along with a co-adapted processing array and compute flow. Resulting methods, systems, devices, and algorithms in accordance with the principles herein overcome many deficiencies in the currently available in—methods, systems, devices, and algorithms (in-SRAM) DNN processing devices. Systems, devices, and algorithms constructed in accordance with the co-adapted implementation herein seamlessly extends to multi-bit precision weights, eliminates the need for DACs, and easily extends to higher vector-scale parallelism. Additionally, a SRAM-immersed successive approximation ADC (SA-ADC) can be constructed, where the parasitic capacitance of bit lines of SRAM array can be exploited as a capacitive DAC. The dominant area overhead in SA-ADC, due to its capacitive DAC, can allow low area implementation of within-SRAM SA-ADC.

Abstract: A memory module system for a high-dimensional weight space neural network configured to process machine learning data streams using Bayesian Inference and/or Classical Inference is set forth. The memory module can include embedded high speed random number generators (RNGs). The memory module is configured to compute, store and sample neural network weights by adapting operating precision to optimize the computing effort based on available weight space and application specifications.