Patents by Inventor Priyono Tri SULISTYANTO
Priyono Tri SULISTYANTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10868198Abstract: A semiconductor device, including an insulator formed on a top surface of a semiconductor substrate, a semiconductor layer, containing a first region of a first conductivity type, formed on the insulator layer, wherein the first region is a P+ region or an N+ region, a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region, wherein the P-N junction comprises a first portion parallel to the top surface of the semiconductor substrate, and the second region is the semiconductor substrate and partially covered by the semiconductor layer, a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.Type: GrantFiled: February 14, 2018Date of Patent: December 15, 2020Assignee: Vanguard International Semiconductor CorporationInventors: Priyono Tri Sulistyanto, Manoj Kumar, Chia-Hao Lee, Chih-Cherng Liao, Shang-Hui Tu
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Publication number: 20180175215Abstract: A semiconductor device, including an insulator formed on a top surface of a semiconductor substrate, a semiconductor layer, containing a first region of a first conductivity type, formed on the insulator layer, wherein the first region is a P+ region or an N+ region, a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region, wherein the P-N junction comprises a first portion parallel to the top surface of the semiconductor substrate, and the second region is the semiconductor substrate and partially covered by the semiconductor layer, a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second regionType: ApplicationFiled: February 14, 2018Publication date: June 21, 2018Applicant: Vanguard International Semiconductor CorporationInventors: Priyono Tri SULISTYANTO, Manoj KUMAR, Chia-Hao LEE, Chih-Cherng LIAO, Shang-Hui TU
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Patent number: 9318601Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer, and a first doped region is disposed in the semiconductor layer adjacent to a first side of the gate structure. A second doped region is disposed in the semiconductor layer adjacent to a second side of the gate structure opposite to the first side. A third doped region is disposed in the first doped region. A fourth doped region is disposed in the second doped region. A plurality of fifth doped regions is disposed in the second doped region. A sixth doped region is disposed in the semiconductor layer under the first doped region. A conductive contact is formed in the third doped region and the first doped region.Type: GrantFiled: June 10, 2014Date of Patent: April 19, 2016Assignee: Vanguard International Semiconductor CorporationInventors: Manoj Kumar, Pei-Heng Hung, Priyono Tri Sulistyanto, Chia-Hao Lee, Chih-Cherng Liao, Shang-Hui Tu
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Publication number: 20160064573Abstract: An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes an insulator formed on a top surface of a semiconductor substrate. The semiconductor device also includes a semiconductor layer containing a first region of a first conductivity type and formed on the insulator layer. The first region is a P+ region or an N+ region and has a volume of over 50-80% of that of the semiconductor layer. The semiconductor device further includes a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region. The second region has a doping concentration heavier than that of the first region. In addition, the semiconductor device includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.Type: ApplicationFiled: August 29, 2014Publication date: March 3, 2016Inventors: Priyono Tri SULISTYANTO, Manoj KUMAR, Chia-Hao LEE, Chih-Cherng LIAO, Shang-Hui TU
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Patent number: 9263436Abstract: A semiconductor device includes: a semiconductor layer; a first doped well region disposed in a portion of the semiconductor layer; a first doped region disposed in the first doped well region; a second doped well region of an asymmetrical cross-sectional profile disposed in another portion of the semiconductor layer; second, third, and fourth doped regions formed in the second doped well region; a first gate structure disposed over a portion of the semiconductor layer, practically covering the second doped well region; and a second gate structure embedded in a portion of the semiconductor layer, penetrating a portion of the second doped well region.Type: GrantFiled: April 30, 2014Date of Patent: February 16, 2016Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Hsiung-Shih Chang, Jui-Chun Chang, Shang-Hui Tu, Priyono Tri Sulistyanto, Chia-Hao Lee
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Publication number: 20150357466Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer, and a first doped region is disposed in the semiconductor layer adjacent to a first side of the gate structure. A second doped region is disposed in the semiconductor layer adjacent to a second side of the gate structure opposite to the first side. A third doped region is disposed in the first doped region. A fourth doped region is disposed in the second doped region. A plurality of fifth doped regions is disposed in the second doped region. A sixth doped region is disposed in the semiconductor layer under the first doped region. A conductive contact is formed in the third doped region and the first doped region.Type: ApplicationFiled: June 10, 2014Publication date: December 10, 2015Inventors: Manoj KUMAR, Pei-Heng HUNG, Priyono Tri SULISTYANTO, Chia-Hao LEE, Chih-Cherng LIAO, Shang-Hui TU
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Publication number: 20150318277Abstract: A semiconductor device includes: a semiconductor layer; a first doped well region disposed in a portion of the semiconductor layer; a first doped region disposed in the first doped well region; a second doped well region of an asymmetrical cross-sectional profile disposed in another portion of the semiconductor layer; second, third, and fourth doped regions formed in the second doped well region; a first gate structure disposed over a portion of the semiconductor layer, practically covering the second doped well region; and a second gate structure embedded in a portion of the semiconductor layer, penetrating a portion of the second doped well region.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Applicant: Vanguard International Semiconductor CorporationInventors: Hsiung-Shih CHANG, Jui-Chun CHANG, Shang-Hui TU, Priyono Tri Sulistyanto, Chia-Hao LEE
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Patent number: 9130033Abstract: The invention provides a semiconductor device, including: a semiconductor device includes: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region, wherein the first conductivity type is opposite to the second conductivity type; and a drain region formed in the drift region; a trench formed in the substrate between the body and drift regions; a gate dielectric layer disposed adjacent to the trench; a liner lining the trench and adjoining with the gate dielectric layer; and a gate electrode formed over the gate dielectric layer and extending into the trench.Type: GrantFiled: December 3, 2013Date of Patent: September 8, 2015Assignee: Vanguard International Semiconductor CorporationInventors: Manoj Kumar, Priyono Tri Sulistyanto, Chia-Hao Lee, Rudy Octavius Sihombing, Shang-Hui Tu
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Patent number: 9076862Abstract: The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer formed over the substrate; wherein the first conductivity type is opposite to the second conductivity type.Type: GrantFiled: February 4, 2013Date of Patent: July 7, 2015Assignee: Vanguard International Semiconductor CorporationInventors: Priyono Tri Sulistyanto, Rudy Octavius Sihombing, Chia-Hao Lee, Shang-Hui Tu
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Publication number: 20150155379Abstract: The invention provides a semiconductor device, including: a semiconductor device includes: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region, wherein the first conductivity type is opposite to the second conductivity type; and a drain region formed in the drift region; a trench formed in the substrate between the body and drift regions; a gate dielectric layer disposed adjacent to the trench; a liner lining the trench and adjoining with the gate dielectric layer; and a gate electrode formed over the gate dielectric layer and extending into the trench.Type: ApplicationFiled: December 3, 2013Publication date: June 4, 2015Applicant: Vanguard International Semiconductor CorporationInventors: Manoj KUMAR, Priyono Tri SULISTYANTO, Chia-Hao LEE, Rudy Octavius SIHOMBING, Shang-Hui TU
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Publication number: 20150137229Abstract: The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region, wherein the first conductivity type is opposite to the second conductivity type; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer having a thick portion formed over the substrate, wherein the gate dielectric includes at least a stepped-shape or a curved shape curved-shape formed thereon, and wherein the multiple RESURF structure is aligned with the thick portion of the gate dielectric layer.Type: ApplicationFiled: November 15, 2013Publication date: May 21, 2015Applicant: Vanguard International Semiconductor CorporationInventors: Priyono Tri SULISTYANTO, Shang-Hui TU
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Publication number: 20140217501Abstract: The invention provides a semiconductor device, including: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region; and a drain region formed in the drift region; a multiple reduced surface field (RESURF) structure embedded in the drift region of the substrate; and a gate dielectric layer formed over the substrate; wherein the first conductivity type is opposite to the second conductivity type.Type: ApplicationFiled: February 4, 2013Publication date: August 7, 2014Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Priyono Tri SULISTYANTO, Rudy Octavius SIHOMBING, Chia-Hao LEE, Shang-Hui TU