Abstract: A device includes a first finite state machine, and a controller coupled to the first finite state machine. The controller is to detect that the first finite state machine fails to perform a first operation within a first duration, and responsive to detecting that the first finite state machine fails to perform the first operation within the first duration, render the first finite state machine available to process a second operation by storing a reset value to a first register associated with the first finite state machine.

Abstract: A system includes a device having a controller a plurality of finite state machines (FSMs). The device is to detect that one or more FSMs of the plurality of FSMs fails to satisfy a non-idle duration criterion during an operation, where the one or more FSM that fail to satisfy the non-idle duration criterion are associated with one or more errors. The device is to determine a location of the one or more FSMs that fail to satisfy the non-idle duration criterion. The device is to record the location of the one or more FSMs and the one or more errors, restore the one or more FSM to an idle state, and transmit an indication that the one or more FSMs failed to satisfy the non-idle duration criterion.

Abstract: A system includes a device having a controller a plurality of finite state machines (FSMs). The device is to detect that one or more FSMs of the plurality of FSMs fails to satisfy a non-idle duration criterion during an operation, where the one or more FSM that fail to satisfy the non-idle duration criterion are associated with one or more errors. The device is to determine a location of the one or more FSMs that fail to satisfy the non-idle duration criterion. The device is to record the location of the one or more FSMs and the one or more errors, restore the one or more FSM to an idle state, and transmit an indication that the one or more FSMs failed to satisfy the non-idle duration criterion.

Abstract: A system, method, and computer program product are provided for hierarchical formal hardware verification of floating-point division and/or square root algorithmic designs using automatic sequential equivalence checking. In use, for at least one of a floating-point division algorithm and a square root algorithm, an architectural specification for hardware, a hardware implementation on the hardware, and at least one intermediate model having a level of specificity between the architectural specification and the hardware implementation are identified. Additionally, an equivalence is automatically determined, hierarchically, between the architectural specification, and the at least one intermediate model, and between the at least one intermediate model and the hardware implementation. Furthermore, for the hardware, the at least one of the floating-point division algorithm and the square root algorithm are formally verified, based on the automatic sequential equivalence determination.

Abstract: A system, method, and computer program product are provided for hierarchical formal hardware verification of floating-point division and/or square root algorithmic designs using automatic sequential equivalence checking. In use, for at least one of a floating-point division algorithm and a square root algorithm, an architectural specification for hardware, a hardware implementation on the hardware, and at least one intermediate model having a level of specificity between the architectural specification and the hardware implementation are identified. Additionally, an equivalence is automatically determined, hierarchically, between the architectural specification, and the at least one intermediate model, and between the at least one intermediate model and the hardware implementation. Furthermore, for the hardware, the at least one of the floating-point division algorithm and the square root algorithm are formally verified, based on the automatic sequential equivalence determination.

Abstract: An efficient and cost effective mechanism for generating test files for automatic verification of a device model is disclosed. Uncompleted coverage goals determined based upon simulating processing of a test file by a design model may be expressed as negative assertions for input to a test data generator, where output from the test data generator may used to create a test file for completing all or some of the uncompleted coverage goals. The test data generator may indicate data which causes a property to fail, and therefore, may indicate test data which causes the uncompleted coverage goal to succeed. The initial test file may represent zero code coverage and/or zero functional coverage, thereby enabling the test data generator to automatically create one or more test files for accomplishing the more extensive code coverage goals and/or functional coverage goals. Functional coverage goals may be automatically generated by the test data generator.

Abstract: An efficient and cost effective mechanism for generating test files for automatic verification of a device model is disclosed. Uncompleted coverage goals determined based upon simulating processing of a test file by a design model may be expressed as negative assertions for input to a test data generator, where output from the test data generator may used to create a test file for completing all or some of the uncompleted coverage goals. The test data generator may indicate data which causes a property to fail, and therefore, may indicate test data which causes the uncompleted coverage goal to succeed. The initial test file may represent zero code coverage and/or zero functional coverage, thereby enabling the test data generator to automatically create one or more test files for accomplishing the more extensive code coverage goals and/or functional coverage goals. Functional coverage goals may be automatically generated by the test data generator.