Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly may include a first semiconductor pillar and a second semiconductor pillar extending vertically from a substrate. The integrated assembly may further include a first epitaxial structure extending vertically from the first semiconductor pillar and a second epitaxial structure extending vertically from the second semiconductor pillar, where the first epitaxial structure is separated from the second epitaxial structure by a gap. The integrated assembly may further include a nitride layer over the first epitaxial structure and the second epitaxial structure, where the nitride layer includes a bridge portion extending between a side portion of the first epitaxial structure and a side portion of the second epitaxial structure.

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a semiconductor substrate and an active region in the semiconductor substrate. The integrated assembly may include a first epitaxial structure on an upper surface of the semiconductor substrate, the first epitaxial structure having a first thickness in a first direction, and a second epitaxial structure on an upper edge of the semiconductor substrate, the second epitaxial structure having a second thickness in a second direction different than the first direction, where the second direction is oblique to the semiconductor substrate, and where the second thickness is less than the first thickness.

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly may include a first semiconductor pillar and a second semiconductor pillar on a semiconductor substrate. The integrated assembly may further include gate oxide material in an isolation region between the first semiconductor pillar and the second semiconductor pillar, the gate oxide material abutting one or more lower sidewalls of the first semiconductor pillar and the second semiconductor pillar. The integrated assembly may further include a socket structure abutting an upper sidewall of the first semiconductor pillar, and the socket structure abutting an upper surface of the first semiconductor pillar.

Abstract: An apparatus comprising a memory array comprising word lines, bit lines, and memory cells, one or more of the memory cells coupled to an associated word line and an associated bit line and comprising active areas and shallow trench isolation (STI) structures adjacent to a base material. The word lines are in the active areas and STI structures and bit line structures are adjacent to the active areas and the STI structures and oriented perpendicular to the word lines. The bit line structures comprise bit lines and bit contacts. Cell contact structures are laterally adjacent to the bit line structures and comprise cell contacts comprising an epitaxial semiconductive material. One or more of the bit contacts and the epitaxial semiconductive material comprise a doped epitaxial silicon material, the doped epitaxial silicon material exhibiting a relatively greater dopant concentration in a [110] crystal orientation than in a [100] or [111] crystal orientation. Methods of forming the apparatus are also disclosed.

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a semiconductor device structure. The semiconductor device structure includes a first semiconductive layer and a multi-layer pad structure over the first semiconductive layer that extending laterally beyond the first semiconductive layer. The multi-layer pad structure includes a second semiconductive layer having at least a portion that is directly on and conjoined with the first semiconductive layer, and compound layer that is directly on and conjoined with the second semiconductive layer and a conductive layer stack that is directly on and conjoined with the compound layer.

Abstract: A method includes forming pillars that project upwardly from a substrate and comprise conductively-doped monocrystalline semiconductive material. The pillars comprise either one source/drain region or another source/drain region of a transistor of individual memory cells of the memory circuitry being formed. Conductively-doped monocrystalline semiconductor material is grown from a top and sidewalls of the pillars to form conductive monocrystalline coverings that are individually directly above the top and circumferentially about the sidewalls of the individual pillars. Digitlines are formed that are individually above and directly electrically coupled to a plurality of the individual pillars of the another source/drain regions through the epitaxially-grown conductive monocrystalline covering that is directly there-above.

Abstract: An electronic device that comprises a source stack comprising one or more conductive materials, a source contact adjacent to the source stack, tiers of alternating conductive materials and dielectric materials adjacent to the source contact, and pillars extending through the tiers and the source contact and into the source stack. At least a portion of the source contact comprises an epitaxial polysilicon material. Electronic systems and methods of forming the electronic device are also disclosed.

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes an elemental region having a first width. The elemental region includes a first native portion of a semiconductive material. The integrated assembly further includes a composite region over the elemental region and having a second width that is greater than or equal to the first width. The composite region includes a second native portion of the semiconductive material that is directly conjoined with the first native portion, and a reconstituted portion of the semiconductive material that is directly conjoined with the second native portion and that extends away from the second native portion.

Abstract: An apparatus comprises a memory array comprising access lines, digit lines, and memory cells. Each memory cell is coupled to an associated access line and an associated digit line and each memory cell comprises an access device, and a monocrystalline semiconductor material adjacent to the access device. A width of the monocrystalline semiconductor material is within a range of from about 8 nm to about 25 nm. Each memory cell comprises a metal silicide material over the monocrystalline semiconductor material, a metal contact material over the metal silicide material, and a storage node adjacent to the metal contact material. Methods of forming an apparatus and systems are also disclosed.

Abstract: A method of forming an apparatus comprises forming a crystalline semiconductor material comprising one or more of a monocrystalline material and a nanocrystalline material adjacent to active areas of memory cells, forming an amorphous material within portions of the crystalline semiconductor material, forming a metal material comprising one or more of chlorine atoms and nitrogen atoms over the amorphous material, converting a portion of the amorphous material and the metal material to form a metal silicide material adjacent to the crystalline semiconductor material, forming cell contacts over the metal silicide material, and forming a storage node adjacent to the cell contacts. Additional methods and apparatus are also disclosed.

Abstract: A method used in forming memory circuitry comprises forming transistors of individual memory cells. The transistors individually comprise one source/drain region and another source/drain region. The one and another source/drain regions comprise conductively-doped monocrystalline semiconductive material. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Masking material is formed directly above the one and another source/drain regions. The masking material has openings there-through that extend to and are individually directly above individual of the one source/drain regions.

Abstract: A magnetic device includes a layer stack comprising a first ferromagnetic layer; a spacer layer on the first ferromagnetic layer; a second ferromagnetic layer on the spacer layer; a dielectric barrier layer on the second ferromagnetic layer; an insertion layer positioned between the second ferromagnetic layer and the dielectric barrier layer; and a fixed layer or an electrode on the dielectric barrier layer. In some examples, a magnetic orientation of the second ferromagnetic layer is switched by a bias voltage across the layer stack without application of an external magnetic field; an antiferromagnetic coupling of the first and second ferromagnetic layers is increased by the bias voltage applying a negative charge to the fixed layer or the electrode, and the antiferromagnetic coupling of the first and second ferromagnetic layers is decreased by the bias voltage applying a positive charge to the fixed layer or the electrode.

Abstract: A magnetic device includes a layer stack comprising a first ferromagnetic layer; a spacer layer on the first ferromagnetic layer; a second ferromagnetic layer on the spacer layer; a dielectric barrier layer on the second ferromagnetic layer; an insertion layer positioned between the second ferromagnetic layer and the dielectric barrier layer; and a fixed layer or an electrode on the dielectric barrier layer. In some examples, a magnetic orientation of the second ferromagnetic layer is switched by a bias voltage across the layer stack without application of an external magnetic field; an antiferromagnetic coupling of the first and second ferromagnetic layers is increased by the bias voltage applying a negative charge to the fixed layer or the electrode, and the antiferromagnetic coupling of the first and second ferromagnetic layers is decreased by the bias voltage applying a positive charge to the fixed layer or the electrode.

Abstract: In some examples, a device includes a dielectric material, a ferromagnetic material, and a topological material positioned between the dielectric material and the ferromagnetic material. The device is configured to trap electric charge inside the dielectric material or at an interface of the dielectric material and the topological material. The device is configured to switch a magnetization state of the ferromagnetic material based on a current through the topological material or based on a voltage in the topological material.

Abstract: A magnetic device may include a layer stack. The layer stack may include a first ferromagnetic layer; a spacer layer on the first ferromagnetic layer; a second ferromagnetic layer on the spacer layer; and a dielectric barrier layer on the second ferromagnetic layer. In some examples, the layer stack may also include an additional ferromagnetic layer and an additional spacer layer. The magnetic device also may include a voltage source configured to apply a bias voltage across the layer stack to cause switching of a magnetic orientation of the second ferromagnetic layer without application of an external magnetic field.

Abstract: A magnetic device may include a layer stack. The layer stack may include a first ferromagnetic layer; a spacer layer on the first ferromagnetic layer; a second ferromagnetic layer on the spacer layer; and a dielectric barrier layer on the second ferromagnetic layer. In some examples, the layer stack may also include an additional ferromagnetic layer and an additional spacer layer. The magnetic device also may include a voltage source configured to apply a bias voltage across the layer stack to cause switching of a magnetic orientation of the second ferromagnetic layer without application of an external magnetic field.

Abstract: In some examples, a device includes a dielectric material, a ferromagnetic material, and a topological material positioned between the dielectric material and the ferromagnetic material. The device is configured to trap electric charge inside the dielectric material or at an interface of the dielectric material and the topological material. The device is configured to switch a magnetization state of the ferromagnetic material based on a current through the topological material or based on a voltage in the topological material.