Patents by Inventor Pu Shan Huang

Pu Shan Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170360
    Abstract: A semiconductor device includes a substrate, an electronic component, a cover and a liquid metal. The electronic component is disposed on the substrate. The cover is disposed on the substrate, coves the electronic component and has a recess. The liquid metal is formed between the recess and the electronic component.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 23, 2024
    Inventors: Chun-Yin LIN, Yu-Jin LI, Tai-Yu CHEN, Pu-Shan HUANG
  • Publication number: 20240145350
    Abstract: A semiconductor device is provided. The semiconductor device includes a carrier, an electronic component, an adapter, a first metal wire and a second metal wire. The electronic component is disposed on the carrier. The adapter is disposed on the carrier. The first metal wire connects the electronic component and the adapter. The second metal wire connects the adapter and the carrier.
    Type: Application
    Filed: September 27, 2023
    Publication date: May 2, 2024
    Inventors: Pu-Shan HUANG, Chi-Yuan CHEN, Shih-Chin LIN
  • Publication number: 20230217591
    Abstract: A board-level pad pattern includes a printed circuit board (PCB) substrate; an exposed pad region disposed within a surface mount region of the base substrate; and multiple staggered ball pads disposed within the surface mount region arranged in a ring shape around the exposed pad region. The staggered ball pads includes first ball pads arranged in a first row and second ball pads arranged in a second row. The first ball pads in the first row are arranged at two different pitches, and the second ball pads in the second row are arranged at a constant pitch. Multiple square-shaped ball pads are arranged in a third row between the exposed pad region and the staggered ball pads.
    Type: Application
    Filed: December 8, 2022
    Publication date: July 6, 2023
    Applicant: MEDIATEK INC.
    Inventors: Hui-Chi Tang, Shao-Chun Ho, Hsuan-Yi Lin, Pu-Shan Huang
  • Publication number: 20230215798
    Abstract: A board-level pad pattern includes a corner pad unit disposed at a corner of a surface mount region for mounting a multi-row QFN package. The corner pad unit includes at least a reversed-L-shaped pad. The reversed-L-shaped pad is disposed in proximity to an apex of the corner of the surface mount region.
    Type: Application
    Filed: December 8, 2022
    Publication date: July 6, 2023
    Applicant: MEDIATEK INC.
    Inventors: Hui-Chi Tang, Shao-Chun Ho, Hsuan-Yi Lin, Pu-Shan Huang
  • Publication number: 20230215797
    Abstract: A board-level pad pattern includes staggered ball pads disposed within a surface mount region for mounting a multi-row QFN package. The staggered ball pads include first ball pads arranged in a first row and second ball pads arranged in a second row. The first ball pads in the first row are arranged at two different pitches, and the second ball pads in the second row are arranged at a constant pitch.
    Type: Application
    Filed: December 6, 2022
    Publication date: July 6, 2023
    Applicant: MEDIATEK INC.
    Inventors: Hui-Chi Tang, Hsuan-Yi Lin, Shao-Chun Ho, Yi-Wen Chiang, Pu-Shan Huang
  • Publication number: 20220165694
    Abstract: A semiconductor structure includes a substrate, a passivation layer on the substrate, a post-passivation interconnect (PPI) structure on the passivation layer, and a polymer layer covering the PPI structure and the passivation layer. The PPI structure includes a step structure disposed on the passivation layer and around a lower edge of the PPI structure.
    Type: Application
    Filed: October 25, 2021
    Publication date: May 26, 2022
    Applicant: MEDIATEK INC.
    Inventor: Pu-Shan Huang
  • Patent number: 10841679
    Abstract: A microelectromechanical systems package structure includes a first substrate, a transducer unit, a semiconductor chip and a second substrate. The first substrate defines a through hole. The transducer unit is electrically connected to the first substrate, and includes a base and a membrane. The membrane is located between the through hole and the base. The semiconductor chip is electrically connected to the first substrate and the transducer unit. The second substrate is attached to the first substrate and defines a cavity. The transducer unit and the chip are disposed in the cavity, and the second substrate is electrically connected to the transducer unit and the semiconductor chip through the first substrate.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 17, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Liang Hsiao, Yu-Hsuan Tsai, Pu Shan Huang, Ching-Han Huang, Lu-Ming Lai
  • Publication number: 20180213312
    Abstract: A microelectromechanical systems package structure includes a first substrate, a transducer unit, a semiconductor chip and a second substrate. The first substrate defines a through hole. The transducer unit is electrically connected to the first substrate, and includes a base and a membrane. The membrane is located between the through hole and the base. The semiconductor chip is electrically connected to the first substrate and the transducer unit. The second substrate is attached to the first substrate and defines a cavity. The transducer unit and the chip are disposed in the cavity, and the second substrate is electrically connected to the transducer unit and the semiconductor chip through the first substrate.
    Type: Application
    Filed: January 24, 2018
    Publication date: July 26, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsu-Liang Hsiao, Yu-Hsuan Tsai, Pu Shan Huang, Ching-Han Huang, Lu-Ming Lai