Patents by Inventor Pucha Zhao

Pucha Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11232727
    Abstract: A substrate, a panel, a detection device and an alignment detection method are provided. The substrate includes first signal connection pins arranged in parallel side by side and at least one first alignment detection pin, wherein the at least one first alignment detection pin is located on at least one side of the first signal connection pins in an arrangement direction of the first signal connection pins, and arranged in parallel with the first signal connection pins.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 25, 2022
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pucha Zhao, Guoqing Zhang, Xiaopeng Bai, Weifeng Wang, Yanbin Dang, Zhixin Guo, Xingliang Wang, Haotian Chen
  • Patent number: 11099226
    Abstract: A test circuitry and a method for testing the same and a test system are provided. The test circuitry includes: a test signal input end, configured to input an initial test signal; a signal output end, configured to output a target test signal; and a signal shaping circuitry coupled to the test signal input end and the signal output end, configured to remove a noise signal from the initial test signal to obtain the target test signal.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: August 24, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Hongwei Gao, Guoqing Zhang, Hongxia Yang, Pucha Zhao, Xiaopeng Bai, Ke Zhao, Zhihui Jia, Yan Zong, Xiaowei Wang, Yaorong Liu
  • Patent number: 11018167
    Abstract: The present disclosure relates to a method and system for performing aging process on the transistor in the display panel. A method for performing aging process on a transistor in a display panel, comprising: obtaining an initial characteristic curve of the transistor; determining an initial cutoff voltage range of the transistor according to the obtained initial characteristic curve; determining a gate-source voltage and a drain-source voltage required by the transistor according to the initial cutoff voltage range, so as to increase an cutoff voltage range of the transistor; and performing aging process on the transistor according to the determined required gate-source voltage and drain-source voltage.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 25, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Ke Zhao, Guoqing Zhang, Hongwei Gao, Xiaowei Wang, Zhihui Jia, Yan Zong, Longfei Yang, Hongxia Yang, Meili Guo, Weifeng Wang, Pucha Zhao, Zhixin Guo
  • Patent number: 10621920
    Abstract: A set of measurement voltages having different voltage values are subsequently inputted to a measurement voltage input terminal of the pixel driving circuit, a light emitting state of a light emitting device under each measurement voltage is detected, and it is determined whether a storage capacitor in the pixel driving circuit is normal based on the light emitting state of the light emitting device.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: April 14, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Hongwei Gao, Xiaowei Wang, Yaorong Liu, Zhihui Jia, Yan Zong, Ke Zhao, Hongxia Yang, Guoqing Zhang, Pucha Zhao, Xiaopeng Bai
  • Patent number: 10510278
    Abstract: The present disclosure provides a signal loading method and a signal generator. The signal loading method includes: loading a first pair of voltage signals to at least one pair of separate signal channels for a time period, respectively, wherein the first pair of voltage signals have a first voltage difference therebetween; and determining whether a short circuit occurs in the at least one pair of signal channels within the time period, and if it is determined that no short circuit occurs in the at least one pair of signal channels within the time period, loading a second pair of voltage signals having a second voltage difference therebetween to the at least one pair of signal channels at the end of the time period. The second voltage difference is greater than the first voltage difference.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: December 17, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Weifeng Wang, Guoqing Zhang, Hongxia Yang, Yu Fu, Xingliang Wang, Zhixin Guo, Yanbin Dang, Xiaowei Wang, Jie Wu, Feiwen Tian, Pucha Zhao, Chenwei Wang, Xuepeng Ji
  • Publication number: 20190311663
    Abstract: A substrate, a panel, a detection device and an alignment detection method are provided. The substrate includes first signal connection pins arranged in parallel side by side and at least one first alignment detection pin, wherein the at least one first alignment detection pin is located on at least one side of the first signal connection pins in an arrangement direction of the first signal connection pins, and arranged in parallel with the first signal connection pins.
    Type: Application
    Filed: October 31, 2018
    Publication date: October 10, 2019
    Inventors: Pucha ZHAO, Guoqing ZHANG, Xiaopeng BAI, Weifeng WANG, Yanbin DANG, Zhixin GUO, Xingliang WANG, Haotian CHEN
  • Publication number: 20190302172
    Abstract: A test circuitry and a method for testing the same and a test system are provided. The test circuitry includes: a test signal input end, configured to input an initial test signal; a signal output end, configured to output a target test signal; and a signal shaping circuitry coupled to the test signal input end and the signal output end, configured to remove a noise signal from the initial test signal to obtain the target test signal.
    Type: Application
    Filed: October 11, 2018
    Publication date: October 3, 2019
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Hongwei GAO, Guoqing ZHANG, Hongxia YANG, Pucha ZHAO, Xiaopeng BAI, Ke ZHAO, Zhihui JIA, Yan ZONG, Xiaowei WANG, Yaorong LIU
  • Patent number: 10412826
    Abstract: The present application discloses a circuit board and a method for manufacturing the same, and a terminal test device. The circuit board includes a base substrate, and a plurality of conductive lines on the base substrate, each of the plurality of conductive lines having one end configured to be connected with a signal output bus of a signal generator and the other end configured to be connected with a terminal. A fuse is connected in series in each conductive line, and a breaking current IT of the fuse, a maximum operating current I of the conductive line and a fault current IF of the conductive line satisfy: I<IT?IF, where the breaking current IT of the fuse is a minimum current that causes the fuse to open.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: September 10, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Pucha Zhao, Guoqing Zhang, Xiaopeng Bai, Hongwei Gao, Weifeng Wang, Yanbin Dang, Haotian Chen
  • Publication number: 20190237019
    Abstract: A set of measurement voltages having different voltage values are subsequently inputted to a measurement voltage input terminal of the pixel driving circuit, a light emitting state of a light emitting device under each measurement voltage is detected, and it is determined whether a storage capacitor in the pixel driving circuit is normal based on the light emitting state of the light emitting device.
    Type: Application
    Filed: September 21, 2018
    Publication date: August 1, 2019
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., Ordos Yuansheng Optoelectronics Co., Ltd.
    Inventors: Hongwei Gao, Xiaowei Wang, Yaorong Liu, Zhihui Jia, Yan Zong, Ke Zhao, Hongxia Yang, Guoqing Zhang, Pucha Zhao, Xiaopeng Bai
  • Publication number: 20190189651
    Abstract: The present disclosure relates to a method and system for performing aging process on the transistor in the display panel. A method for performing aging process on a transistor in a display panel, comprising: obtaining an initial characteristic curve of the transistor; determining an initial cutoff voltage range of the transistor according to the obtained initial characteristic curve; determining a gate-source voltage and a drain-source voltage required by the transistor according to the initial cutoff voltage range, so as to increase an cutoff voltage range of the transistor; and performing aging process on the transistor according to the determined required gate-source voltage and drain-source voltage.
    Type: Application
    Filed: August 2, 2018
    Publication date: June 20, 2019
    Inventors: Ke ZHAO, Guoqing ZHANG, Hongwei GAO, Xiaowei WANG, Zhihui JIA, Yan ZONG, Longfei YANG, Hongxia YANG, Meili GUO, Weifeng WANG, Pucha ZHAO, Zhixin GUO
  • Publication number: 20190180662
    Abstract: The present disclosure provides a signal loading method and a signal generator. The signal loading method includes: loading a first pair of voltage signals to at least one pair of separate signal channels for a time period, respectively, wherein the first pair of voltage signals have a first voltage difference therebetween; and determining whether a short circuit occurs in the at least one pair of signal channels within the time period, and if it is determined that no short circuit occurs in the at least one pair of signal channels within the time period, loading a second pair of voltage signals having a second voltage difference therebetween to the at least one pair of signal channels at the end of the time period. The second voltage difference is greater than the first voltage difference.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Inventors: Weifeng WANG, Guoqing ZHANG, Hongxia YANG, Yu FU, Xingliang WANG, Zhixin GUO, Yanbin DANG, Xiaowei WANG, Jie WU, Feiwen TIAN, Pucha ZHAO, Chenwei WANG, Xuepeng JI
  • Patent number: 10229619
    Abstract: Embodiments of the present disclosure provide a test circuit, a test method, a display panel and a display apparatus. Each of the signal input terminals may input a plurality of signals in a time division multiplexed manner, and in turn may be controlled by the corresponding switches to form a plurality of signal lines, a signal flow of the plurality of signal lines are totally different from each other under control of the switches. For example, one of the signal lines may function as a signal input line, and the other one of the signal lines may function as a signal input line for other specific testing, such as aging process so as to input signals different from the normal turn-on state signals. Consequently, by controlling the corresponding switches through the control signal terminals so that different input signals pass through different signal lines into the display panel to meet testing requirements of normal turn-on state testing, aging process and so on for the display panel.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: March 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Yuebai Han, Xinxin Jin, Xiaopeng Bai, Shanshan Bao, Pucha Zhao, Jin Zhao, Hongwei Gao, Mingyang Zhang, Tao Yang
  • Publication number: 20190075650
    Abstract: The present application discloses a circuit board and a method for manufacturing the same, and a terminal test device. The circuit board includes a base substrate, and a plurality of conductive lines on the base substrate, each of the plurality of conductive lines having one end configured to be connected with a signal output bus of a signal generator and the other end configured to be connected with a terminal. A fuse is connected in series in each conductive line, and a breaking current IT of the fuse, a maximum operating current I of the conductive line and a fault current IF of the conductive line satisfy: I<IT?IF, where the breaking current IT of the fuse is a minimum current that causes the fuse to open.
    Type: Application
    Filed: April 3, 2018
    Publication date: March 7, 2019
    Inventors: Pucha ZHAO, Guoqing ZHANG, Xiaopeng BAI, Hongwei GAO, Weifeng WANG, Yanbin DANG, Haotian CHEN
  • Publication number: 20170200404
    Abstract: Embodiments of the present disclosure provide a test circuit, a test method, a display panel and a display apparatus. Each of the signal input terminals may input a plurality of signals in a time division multiplexed manner, and in turn may be controlled by the corresponding switches to form a plurality of signal lines, a signal flow of the plurality of signal lines are totally different from each other under control of the switches. For example, one of the signal lines may function as a signal input line, and the other one of the signal lines may function as a signal input line for other specific testing, such as aging process so as to input signals different from the normal turn-on state signals. Consequently, by controlling the corresponding switches through the control signal terminals so that different input signals pass through different signal lines into the display panel to meet testing requirements of normal turn-on state testing, aging process and so on for the display panel.
    Type: Application
    Filed: August 5, 2016
    Publication date: July 13, 2017
    Inventors: Yuebai Han, Xinxin Jin, Xiaopeng Bai, Shanshan Bao, Pucha Zhao, Jin Zhao, Hongwei Gao, Mingyang Zhang, Tao Yang