Abstract: A modified branch metric for decoders and equalizers is described. In one embodiment the branch metric includes determining a set of branch metric values for symbols of a received digital signal, the branch metric values indicating a correlation between symbols obtained using a reduced calculation set, the reduced calculation set being obtained by adding a common term to all of the branch metric values before determining the correlation. The branch metric may be followed by determining path metrics for paths through a decision tree using the branch metric values, and selecting a path and a corresponding symbol sequence in the received digital signal using the path metric values.

Abstract: According to an embodiment of the invention, a method and apparatus are described for producing an error word for a data stream. According to an embodiment of the invention, a method includes receiving a plurality of data elements of a data stream; and updating an error word for the data stream by processing the plurality of data elements in a single iteration.

Abstract: According to an embodiment of the invention, a method and apparatus are described for error detection for multi-stream communication. Under an embodiment of the invention, a method for producing an error word for a data stream comprises computing an intermediate error word for each of a plurality of data sub-streams, the data stream being equivalent to a concatenation of the plurality of data sub-streams; and combining the intermediate error words to produce the error word for the data stream.

Abstract: In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform (“FHT”) engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can further include a controller to correlate the received input sequence with a plurality of Walsh-Hadamard codewords using two add/subtract modules. In one embodiment, the two add/subtract modules operate in parallel.

Abstract: In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform (“FHT”) engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can further include a controller to correlate the received input sequence with a plurality of Walsh-Hadamard codewords using two add/subtract modules. In one embodiment, the two add/subtract modules operate in parallel.

Abstract: According to an embodiment of the invention, a method and apparatus are described for producing an error word for a data stream. According to an embodiment of the invention, a method comprises receiving a plurality of data elements of a data stream; and updating an error word for the data stream by processing the plurality of data elements in a single iteration.

Abstract: According to an embodiment of the invention, a method and apparatus are described for error detection for multi-stream communication. Under an embodiment of the invention, a method for producing an error word for a data stream comprises computing an intermediate error word for each of a plurality of data sub-streams, the data stream being equivalent to a concatenation of the plurality of data sub-streams; and combining the intermediate error words to produce the error word for the data stream.

Abstract: The present invention allows a complex digital processing engine to be tested automatically and autonomously using a minimum of memory and processing resources. In one embodiment, the invention includes a test controller integrated on an IC, a test pattern generator coupled to the controller to provide a test pattern upon receiving a controller command, and a unit under test integrated on the IC coupled to the test controller to receive a start signal from the test controller to apply an operation to the test pattern, the operation generating a test output. It further includes a test buffer integrated on the IC coupled to the unit under test to receive and store a representation of the test output, a reference memory integrated on the IC to store a reference value, and a comparator integrated on the IC coupled to the test controller to compare the test buffer contents to the stored reference value and to provide a test result signal to the test.

Abstract: The present invention allows a complex digital processing engine to be tested automatically and autonomously using a minimum of memory and processing resources. In one embodiment, the invention includes an input buffer to store a digital test sequence, a digital data modulator coupled to the input buffer to generate a modulated digital sample sequence using the test sequence, a test buffer coupled to the modulator to receive and store a representation of the sample sequence, and a test buffer output to enable the test buffer contents to be compared to a reference sequence.