Patents by Inventor PULKIT AGARWAL
PULKIT AGARWAL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10978302Abstract: A method for forming features over a wafer with a carbon based deposition is provided. The carbon based deposition is pretuned, wherein the pretuning causes a non-uniform removal of some of the carbon based deposition. An oxide deposition of a silicon oxide based material is deposited through an atomic layer deposition process, wherein the depositing the oxide deposition causes a non-uniform removal of some of the carbon based deposition, which is complementary to the non-uniform removal of some of the carbon based deposition by the pretuning.Type: GrantFiled: May 8, 2018Date of Patent: April 13, 2021Assignee: Lam Research CorporationInventors: Ishtak Karim, Pulkit Agarwal, Joseph Abel, Purushottam Kumar, Adrien Lavoie
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Publication number: 20200407847Abstract: An apparatus for processing stacks is provided. A first gas source is provided. A first gas manifold is connected to the first gas source. A first processing station has a first gas outlet, wherein the first gas outlet is connected to the first gas manifold. A first variable conductance valve is between the first gas source and the first gas outlet along the first gas manifold.Type: ApplicationFiled: September 14, 2020Publication date: December 31, 2020Inventors: Adrien LAVOIE, Pulkit AGARWAL
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Patent number: 10847352Abstract: A controller includes memory that stores data correlating accumulation values to respective adjustment factors. The accumulation values correspond to accumulation of material on surfaces within a processing chamber and the respective adjustment factors correspond to adjustments to a control parameter of RF power provided to the processing chamber. An accumulation calculation module is configured to calculate a first accumulation value indicating an amount of accumulation of the material. An RF power control module is configured to receive the first accumulation value, receive at least one of a setpoint power and a duration of an etching step, retrieve the stored data from the memory, adjust the control parameter based on the first accumulation value, the at least one of the setpoint power and the duration of the etching step, and the stored data, and control the RF power provided to the processing chamber in accordance with the adjusted control parameter.Type: GrantFiled: August 2, 2018Date of Patent: November 24, 2020Assignee: LAM RESEARCH CORPORATIONInventors: Pulkit Agarwal, Adrien Lavoie, Ravi Kumar, Purushottam Kumar
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Publication number: 20200356866Abstract: Methods and apparatus, including computer program products, implementing and using techniques for generating a recommendation for a composite computer application program from unstructured text. Unstructured text specifying functional requirements for a composite computer application program is received. The unstructured text is processed to generate topic metadata. The topics represent actions to be performed by the composite computer application program. Based on the generated topic metadata, a micro service is determined for performing each action. A recommendation for a sequence of microservices pertinent to the specified functional requirements is also determined, wherein each microservice is deployed in a separate container. Rules for synchronizing operations between the individual containers are specified. A recommendation for a deployable composite computer application program comprising the collection of individual containers and the specified rules is generated.Type: ApplicationFiled: May 8, 2019Publication date: November 12, 2020Inventors: Santanu Chakrabarty, Pulkit Agarwal, Ajitha Chandran, Sivaraj Sethunamasivayam, SIVARANJANI KATHIRVEL
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Publication number: 20200350219Abstract: A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.Type: ApplicationFiled: July 21, 2020Publication date: November 5, 2020Inventors: Pulkit Agarwal, Adrien LaVoie, Ravi Kumar, Purushottam Kumar
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Patent number: 10801109Abstract: An apparatus for processing substrates is provided. A first gas source is provided. A first gas manifold is connected to the first gas source. A second gas manifold is connected to the first gas source. A first processing station has a first gas outlet, wherein the first gas outlet is connected to the first gas manifold. A second processing station has a second gas outlet, wherein the second gas outlet is connected to the second gas manifold. A first variable conductance valve is between the first gas source and the first gas outlet along the first gas manifold. A second variable conductance valve is between the first gas source and the second gas outlet along the second gas manifold.Type: GrantFiled: August 29, 2018Date of Patent: October 13, 2020Assignee: Lam Research CorporationInventors: Adrien Lavoie, Pulkit Agarwal
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Patent number: 10727143Abstract: A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.Type: GrantFiled: July 24, 2018Date of Patent: July 28, 2020Assignee: Lam Research CorporationInventors: Pulkit Agarwal, Adrien Lavoie, Ravi Kumar, Purushottam Kumar
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Publication number: 20200230782Abstract: Embodiments of methods and apparatus for cleaning contaminants from a substrate are disclosed herein. In some embodiments, a substrate cleaning apparatus includes: a substrate support to support a substrate along an edge of the substrate, wherein the substrate further includes a first side and an opposing second side having contaminants disposed on the second side; a showerhead disposed a first distance of about 1.5 mm to about 4.4 mm opposite the substrate support and facing the first side of the substrate; and one or more nozzles disposed a second distance of about 1 inch to about 2 inches beneath the substrate support to discharge a mixture of solid and gaseous carbon dioxide toward the contaminants on the second side of the substrate, and wherein the one or more nozzles have an angle of about 20 to about 40 degrees.Type: ApplicationFiled: April 2, 2020Publication date: July 23, 2020Inventors: Pulkit AGARWAL, Bonnie T. CHIA, Song-Moon SUH, Cheng-Hsiung TSAI, Dhritiman Subha KASHYAP, Xiaoxiong YUAN, Eric RIESKE
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Patent number: 10655224Abstract: A semiconductor system includes a chamber, a pedestal disposed in the chamber, and a focus ring that surrounds the pedestal. The pedestal has a center region for supporting a central region of a substrate, e.g., a wafer. The focus ring is configured to surround the center region of the pedestal. The focus ring has an annular support region that extends between an inner portion of the focus ring and an outer portion of the focus ring. The annular support region, which is disposed at an angle relative to a horizontal line, provides a knife-edge contact for the substrate when present over the center region of the pedestal and the annular support region of the focus ring. The knife-edge contact between the edge of the substrate and the annular support region of the focus ring disables chemical access to the substrate backside and thereby reduces unwanted backside deposition.Type: GrantFiled: December 20, 2016Date of Patent: May 19, 2020Assignee: Lam Research CorporationInventors: Pulkit Agarwal, Ishtak Karim, Purushottam Kumar, Adrien LaVoie, Sung Je Kim, Patrick Breiling
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Patent number: 10658172Abstract: Methods and apparatuses for depositing material into high aspect ratio features, features in a multi-laminate stack, features having positively sloped sidewalls, features having negatively sloped sidewalls, features having a re-entrant profile, and/or features having sidewall topography are described herein. Methods involve depositing a first amount of material, such as a dielectric (e.g., silicon oxide), into a feature and forming a sacrificial helmet on the field surface of the substrate, etching some of the first amount of the material to open the feature opening and/or smoothen sidewalls of the feature, and depositing a second amount of material to fill the feature. The sacrificial helmet may be the same as or different material from the first amount of material deposited into the feature.Type: GrantFiled: March 6, 2019Date of Patent: May 19, 2020Assignee: Lam Research CorporationInventors: Joseph R. Abel, Pulkit Agarwal, Richard Phillips, Purushottam Kumar, Adrien LaVoie
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Publication number: 20200071826Abstract: An apparatus for processing substrates is provided. A first gas source is provided. A first gas manifold is connected to the first gas source. A second gas manifold is connected to the first gas source. A first processing station has a first gas outlet, wherein the first gas outlet is connected to the first gas manifold. A second processing station has a second gas outlet, wherein the second gas outlet is connected to the second gas manifold. A first variable conductance valve is between the first gas source and the first gas outlet along the first gas manifold. A second variable conductance valve is between the first gas source and the second gas outlet along the second gas manifold.Type: ApplicationFiled: August 29, 2018Publication date: March 5, 2020Inventors: Adrien LAVOIE, Pulkit AGARWAL
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Patent number: 10579371Abstract: In creating recommendations for software upgrades in a computing system, a natural language processing module of a software upgrade analyzer system receives risk analysis reports and a corresponding current application source code. The natural language processing module processes the risk analysis report and the current application source code to identify an application programming interface (API) key set containing key terms. A support vector machine of the software upgrade analyzer system identifies key terms in the API key set. An association rule mining module of the software upgrade analyzer system calculates a support factor and a confidence factor for each key term combination of the key terms. The association rule mining module identifies a highest ranking key term combination based on the confidence factor for each key term combination. The software upgrade analyzer system outputs the highest ranking key term combination as a software upgrade recommendation.Type: GrantFiled: December 13, 2017Date of Patent: March 3, 2020Assignee: International Business Machines CorporationInventors: Pulkit Agarwal, Santanu Chakrabarty, Sivaranjani Kathirvel, Sivaraj Sethunamasivayam
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Publication number: 20200063259Abstract: A method for processing a substrate is provided, wherein the substrate is located below a showerhead in a processing chamber. A deposition layer is deposited on the substrate, wherein at least one deposition gas is provided through the showerhead. A secondary purge gas is flowed during the depositing the deposition layer from a location outside of the showerhead in the processing chamber forming a flow curtain around an outer edge of the showerhead, wherein the secondary purge gas comprises at least one component gas. A partial pressure of the at least one component gas is changed over time during the depositing the deposition layer, wherein the depositing the deposition layer has a non-uniformity, wherein the changing the partial pressure changes the non-uniformity over time during the depositing the deposition layer.Type: ApplicationFiled: August 22, 2018Publication date: February 27, 2020Inventors: Pulkit AGARWAL, Adrien LAVOIE, Purushottam KUMAR
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Publication number: 20200043709Abstract: A controller includes memory that stores data correlating accumulation values to respective adjustment factors. The accumulation values correspond to accumulation of material on surfaces within a processing chamber and the respective adjustment factors correspond to adjustments to a control parameter of RF power provided to the processing chamber. An accumulation calculation module is configured to calculate a first accumulation value indicating an amount of accumulation of the material. An RF power control module is configured to receive the first accumulation value, receive at least one of a setpoint power and a duration of an etching step, retrieve the stored data from the memory, adjust the control parameter based on the first accumulation value, the at least one of the setpoint power and the duration of the etching step, and the stored data, and control the RF power provided to the processing chamber in accordance with the adjusted control parameter.Type: ApplicationFiled: August 2, 2018Publication date: February 6, 2020Inventors: Pulkit Agarwal, Adrien Lavoie, Ravi Kumar, Purushottam Kumar
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Publication number: 20200035572Abstract: A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.Type: ApplicationFiled: July 24, 2018Publication date: January 30, 2020Inventors: Pulkit Agarwal, Adrien Lavoie, Ravi Kumar, Purushottam Kumar
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Publication number: 20200002815Abstract: A method for adjusting a position of a showerhead in a processing chamber includes arranging a substrate that includes a plurality of mandrels on a substrate support in the processing chamber and adjusting a position of the showerhead relative to the substrate support. Adjusting the position of the showerhead includes adjusting the showerhead to a tilted position based on data indicating a correlation between the position of the showerhead and azimuthal non-uniformities associated with etching the substrate. The method further includes, with the showerhead in the tilted position as adjusted based on the data, performing a trim step to etch the plurality of mandrels.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Pulkit AGARWAL, Adrien LAVOIE, Frank Loren PASQUALE, Ravi KUMAR
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Patent number: 10494715Abstract: Methods and apparatuses for removing photoresist patterning scum from patterning mandrel structures without damaging other features or structures on a semiconductor substrate are desirable for patterning precision. Methods involve cleaning carbon-containing features on a semiconductor substrate by an atomic layer cleaning (ALC) process to descum the carbon-containing features without substantially modifying feature critical dimensions. The ALC process involves exposing the carbon-containing features to an oxidant or reductant in absence of a plasma, or other energetic activation, to modify scum on the surface of the carbon-containing features. The modified scum on the surface of the carbon-containing features is then exposed to an inert gas along with a plasma ignited at a pressure between 0.1 Torr and 10 Torr and a power of less than 200 W to remove the modified scum from the surface of the carbon-containing features.Type: GrantFiled: July 19, 2017Date of Patent: December 3, 2019Assignee: LAM RESEARCH CORPORATIONInventors: Pulkit Agarwal, Purushottam Kumar, Adrien LaVoie
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Publication number: 20190345608Abstract: A method for depositing a layer on a substrate is provided. A plurality of plasma atomic layer deposition (ALD) layers is deposited over the substrate, wherein each plasma ALD layer of the plurality of ALD layers is deposited at a first RF power. The plurality of plasma ALD layers is densified, comprising generating a densifying plasma using a second RF power greater than the first RF power, wherein at least one of the plurality of plasma ALD layers is densified.Type: ApplicationFiled: May 8, 2018Publication date: November 14, 2019Inventors: Pulkit AGARWAL, Purushottam KUMAR, Adrien LAVOIE
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Patent number: 10431489Abstract: Embodiments of apparatus for supporting a substrate are disclosed herein. In some embodiments, an apparatus for supporting a substrate includes: a support surface; and a plurality of substrate contact elements protruding from the support surface, wherein the plurality of substrate contact elements are formed of a material having a hardness less than or equal to a hardness of silicon, having a low adhesion, having a coefficient of static friction large enough to prevent sliding, having a surface roughness less than or equal to 10 Ra, and that is electrically conductive.Type: GrantFiled: November 26, 2014Date of Patent: October 1, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Pulkit Agarwal, Song-Moon Suh, Glen Mori, Steven V. Sansoni
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Patent number: 10431451Abstract: Certain embodiments herein relate to methods of increasing a reaction chamber batch size. A portion of a batch of wafers is processed within the chamber. The processing results in at least some off-target deposition of material on interior surfaces of the reaction chamber. A mid-batch chamber processing is conducted to stabilize the off-target deposition materials accumulated on the chamber interior surfaces. Another portion of the batch of wafers is processed within the chamber. In various embodiments, processing of the chamber (e.g., mid-batch) and subsequent portion of the batch of wafers is repeated until processing of all wafers is complete. Batch size refers to the number of wafers that may be processed in the reaction chamber between chamber clean cycles. Chamber interior surfaces are seasoned prior to batch processing. Seasoning of the chamber interior surfaces involves applying a coating of the same material that may be used for deposition on the wafers during processing of the same.Type: GrantFiled: October 31, 2017Date of Patent: October 1, 2019Assignee: LAM RESEARCH CORPORATIONInventors: Pulkit Agarwal, Purushottam Kumar, Richard Phillips, Adrien LaVoie