Abstract: One or more embodiments of the present disclosure relate to determining a first execution schedule for execution of a plurality of runnables, the plurality of runnables corresponding to a process executed using a plurality of compute engines. Additionally or alternatively, one or more embodiments may relate to modifying the first execution schedule to generate a second execution schedule. The modifying may include moving one or more runnables of the plurality of runnables to populate one or more gaps in the first execution schedule. The moving of the one or more runnables may be performed in view of one or more moving constraints.

Abstract: One or more embodiments of the present disclosure relate to monitoring execution of runnables that may be executed by a computing system, the executing begin based at least on a schedule. The monitoring may include one or more of: monitoring timing of execution of the runnables, monitoring one or more sequences of execution of the runnables, or monitoring health of at least a portion of the computing system executing the runnables. Additionally or alternatively, one or more embodiments may relate to determining compliance with respect to one or more execution constraints based at least in part on the monitoring.

Abstract: One or more embodiments of the present disclosure relate to executing, by a plurality of compute engines, a plurality of runnables of a computing application based at least on an execution schedule and a set of commands associated with the execution schedule. The execution schedule may be generated using a compiling system to include the set of commands. The set of commands may include one or more individual commands corresponding to one or more timing fences dictating a timing and order of execution of one or more individual runnables of the plurality of runnables.

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract: A technique for managing memory allocation in an electronic device is provided. In one embodiment, a method includes loading a memory allocation strategy for an application executed by a processor of a device, and requesting memory for the application from various memory locations in accordance with the memory allocation strategy. In one embodiment, the device includes multiple sets of contiguous memory blocks and a memory heap, memory may be requested from at least one of these memory locations, and memory may then be allocated to the application in response to the request. In some embodiments, the memory allocation strategy may be stored in the device prior to execution of the application. Various other methods, devices, and manufactures are also provided.

Abstract: A technique for managing memory allocation in an electronic device is provided. In one embodiment, a method includes loading a memory allocation strategy for an application executed by a processor of a device, and requesting memory for the application from various memory locations in accordance with the memory allocation strategy. In one embodiment, the device includes multiple sets of contiguous memory blocks and a memory heap, memory may be requested from at least one of these memory locations, and memory may then be allocated to the application in response to the request. In some embodiments, the memory allocation strategy may be stored in the device prior to execution of the application. Various other methods, devices, and manufactures are also provided.